Commit 63df37f3 authored by Nicolas Frattaroli's avatar Nicolas Frattaroli Committed by Yury Norov
Browse files

drm/rockchip: dw_hdmi: switch to FIELD_PREP_WM16* macros 



The era of hand-rolled HIWORD_UPDATE macros is over, at least for those
drivers that use constant masks.

Remove this driver's very own HIWORD_UPDATE macro, and replace all
instances of it with equivalent instantiations of FIELD_PREP_WM16 or
FIELD_PREP_WM16_CONST, depending on whether it's in an initializer.

This gives us better error checking, and a centrally agreed upon
signature for this macro, to ease in code comprehension.

Because FIELD_PREP_WM16/FIELD_PREP_WM16_CONST shifts the value to the
mask (like FIELD_PREP et al do), a lot of macro instantiations get
easier to read.

This was tested on an RK3568 ODROID M1, as well as an RK3399 ROCKPro64.

Reviewed-by: default avatarCristian Ciocaltea <cristian.ciocaltea@collabora.com>
Tested-by: default avatarCristian Ciocaltea <cristian.ciocaltea@collabora.com>
Signed-off-by: default avatarNicolas Frattaroli <nicolas.frattaroli@collabora.com>
Reviewed-by: default avatarHeiko Stuebner <heiko@sntech.de>
Signed-off-by: default avatarYury Norov (NVIDIA) <yury.norov@gmail.com>
parent a104de64

drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c

+36 −44
Original line number Diff line number Diff line
@@ -4,6 +4,7 @@ 
 */



#include <linux/clk.h>

#include <linux/hw_bitfield.h>

#include <linux/mfd/syscon.h>

#include <linux/module.h>

#include <linux/platform_device.h>
@@ -54,8 +55,6 @@ 
#define RK3568_HDMI_SDAIN_MSK		BIT(15)

#define RK3568_HDMI_SCLIN_MSK		BIT(14)



#define HIWORD_UPDATE(val, mask)	(val | (mask) << 16)



/**

 * struct rockchip_hdmi_chip_data - splite the grf setting of kind of chips

 * @lcdsel_grf_reg: grf register offset of lcdc select
@@ -355,17 +354,14 @@ static void dw_hdmi_rk3228_setup_hpd(struct dw_hdmi *dw_hdmi, void *data) 


	dw_hdmi_phy_setup_hpd(dw_hdmi, data);



	regmap_write(hdmi->regmap,

		RK3228_GRF_SOC_CON6,

		HIWORD_UPDATE(RK3228_HDMI_HPD_VSEL | RK3228_HDMI_SDA_VSEL |

			      RK3228_HDMI_SCL_VSEL,

			      RK3228_HDMI_HPD_VSEL | RK3228_HDMI_SDA_VSEL |

			      RK3228_HDMI_SCL_VSEL));



	regmap_write(hdmi->regmap,

		RK3228_GRF_SOC_CON2,

		HIWORD_UPDATE(RK3228_HDMI_SDAIN_MSK | RK3228_HDMI_SCLIN_MSK,

			      RK3228_HDMI_SDAIN_MSK | RK3228_HDMI_SCLIN_MSK));

	regmap_write(hdmi->regmap, RK3228_GRF_SOC_CON6,

		     FIELD_PREP_WM16(RK3228_HDMI_HPD_VSEL, 1) |

		     FIELD_PREP_WM16(RK3228_HDMI_SDA_VSEL, 1) |

		     FIELD_PREP_WM16(RK3228_HDMI_SCL_VSEL, 1));



	regmap_write(hdmi->regmap, RK3228_GRF_SOC_CON2,

		     FIELD_PREP_WM16(RK3228_HDMI_SDAIN_MSK, 1) |

		     FIELD_PREP_WM16(RK3328_HDMI_SCLIN_MSK, 1));

}



static enum drm_connector_status
@@ -377,15 +373,13 @@ dw_hdmi_rk3328_read_hpd(struct dw_hdmi *dw_hdmi, void *data) 
	status = dw_hdmi_phy_read_hpd(dw_hdmi, data);



	if (status == connector_status_connected)

		regmap_write(hdmi->regmap,

			RK3328_GRF_SOC_CON4,

			HIWORD_UPDATE(RK3328_HDMI_SDA_5V | RK3328_HDMI_SCL_5V,

				      RK3328_HDMI_SDA_5V | RK3328_HDMI_SCL_5V));

		regmap_write(hdmi->regmap, RK3328_GRF_SOC_CON4,

			     FIELD_PREP_WM16(RK3328_HDMI_SDA_5V, 1) |

			     FIELD_PREP_WM16(RK3328_HDMI_SCL_5V, 1));

	else

		regmap_write(hdmi->regmap,

			RK3328_GRF_SOC_CON4,

			HIWORD_UPDATE(0, RK3328_HDMI_SDA_5V |

					 RK3328_HDMI_SCL_5V));

		regmap_write(hdmi->regmap, RK3328_GRF_SOC_CON4,

			     FIELD_PREP_WM16(RK3328_HDMI_SDA_5V, 0) |

			     FIELD_PREP_WM16(RK3328_HDMI_SCL_5V, 0));

	return status;

}
@@ -396,21 +390,21 @@ static void dw_hdmi_rk3328_setup_hpd(struct dw_hdmi *dw_hdmi, void *data) 
	dw_hdmi_phy_setup_hpd(dw_hdmi, data);



	/* Enable and map pins to 3V grf-controlled io-voltage */

	regmap_write(hdmi->regmap,

		RK3328_GRF_SOC_CON4,

		HIWORD_UPDATE(0, RK3328_HDMI_HPD_SARADC | RK3328_HDMI_CEC_5V |

				 RK3328_HDMI_SDA_5V | RK3328_HDMI_SCL_5V |

				 RK3328_HDMI_HPD_5V));

	regmap_write(hdmi->regmap,

		RK3328_GRF_SOC_CON3,

		HIWORD_UPDATE(0, RK3328_HDMI_SDA5V_GRF | RK3328_HDMI_SCL5V_GRF |

				 RK3328_HDMI_HPD5V_GRF |

				 RK3328_HDMI_CEC5V_GRF));

	regmap_write(hdmi->regmap,

		RK3328_GRF_SOC_CON2,

		HIWORD_UPDATE(RK3328_HDMI_SDAIN_MSK | RK3328_HDMI_SCLIN_MSK,

			      RK3328_HDMI_SDAIN_MSK | RK3328_HDMI_SCLIN_MSK |

			      RK3328_HDMI_HPD_IOE));

	regmap_write(hdmi->regmap, RK3328_GRF_SOC_CON4,

		     FIELD_PREP_WM16(RK3328_HDMI_HPD_SARADC, 0) |

		     FIELD_PREP_WM16(RK3328_HDMI_CEC_5V, 0) |

		     FIELD_PREP_WM16(RK3328_HDMI_SDA_5V, 0) |

		     FIELD_PREP_WM16(RK3328_HDMI_SCL_5V, 0) |

		     FIELD_PREP_WM16(RK3328_HDMI_HPD_5V, 0));

	regmap_write(hdmi->regmap, RK3328_GRF_SOC_CON3,

		     FIELD_PREP_WM16(RK3328_HDMI_SDA5V_GRF, 0) |

		     FIELD_PREP_WM16(RK3328_HDMI_SCL5V_GRF, 0) |

		     FIELD_PREP_WM16(RK3328_HDMI_HPD5V_GRF, 0) |

		     FIELD_PREP_WM16(RK3328_HDMI_CEC5V_GRF, 0));

	regmap_write(hdmi->regmap, RK3328_GRF_SOC_CON2,

		     FIELD_PREP_WM16(RK3328_HDMI_SDAIN_MSK, 1) |

		     FIELD_PREP_WM16(RK3328_HDMI_SCLIN_MSK, 1) |

		     FIELD_PREP_WM16(RK3328_HDMI_HPD_IOE, 0));



	dw_hdmi_rk3328_read_hpd(dw_hdmi, data);

}
@@ -438,8 +432,8 @@ static const struct dw_hdmi_plat_data rk3228_hdmi_drv_data = { 


static struct rockchip_hdmi_chip_data rk3288_chip_data = {

	.lcdsel_grf_reg = RK3288_GRF_SOC_CON6,

	.lcdsel_big = HIWORD_UPDATE(0, RK3288_HDMI_LCDC_SEL),

	.lcdsel_lit = HIWORD_UPDATE(RK3288_HDMI_LCDC_SEL, RK3288_HDMI_LCDC_SEL),

	.lcdsel_big = FIELD_PREP_WM16_CONST(RK3288_HDMI_LCDC_SEL, 0),

	.lcdsel_lit = FIELD_PREP_WM16_CONST(RK3288_HDMI_LCDC_SEL, 1),

	.max_tmds_clock = 340000,

};
@@ -475,8 +469,8 @@ static const struct dw_hdmi_plat_data rk3328_hdmi_drv_data = { 


static struct rockchip_hdmi_chip_data rk3399_chip_data = {

	.lcdsel_grf_reg = RK3399_GRF_SOC_CON20,

	.lcdsel_big = HIWORD_UPDATE(0, RK3399_HDMI_LCDC_SEL),

	.lcdsel_lit = HIWORD_UPDATE(RK3399_HDMI_LCDC_SEL, RK3399_HDMI_LCDC_SEL),

	.lcdsel_big = FIELD_PREP_WM16_CONST(RK3399_HDMI_LCDC_SEL, 0),

	.lcdsel_lit = FIELD_PREP_WM16_CONST(RK3399_HDMI_LCDC_SEL, 1),

	.max_tmds_clock = 594000,

};
@@ -589,10 +583,8 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master, 


	if (hdmi->chip_data == &rk3568_chip_data) {

		regmap_write(hdmi->regmap, RK3568_GRF_VO_CON1,

			     HIWORD_UPDATE(RK3568_HDMI_SDAIN_MSK |

					   RK3568_HDMI_SCLIN_MSK,

					   RK3568_HDMI_SDAIN_MSK |

					   RK3568_HDMI_SCLIN_MSK));

			     FIELD_PREP_WM16(RK3568_HDMI_SDAIN_MSK, 1) |

			     FIELD_PREP_WM16(RK3568_HDMI_SCLIN_MSK, 1));

	}



	drm_encoder_helper_add(encoder, &dw_hdmi_rockchip_encoder_helper_funcs);