Unverified Commit 63f93a3c authored by Clément Léger's avatar Clément Léger Committed by Palmer Dabbelt
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riscv: hwprobe: export Zihintpause ISA extension 



Export the Zihintpause ISA extension through hwprobe which allows using
"pause" instructions. Some userspace applications (OpenJDK for
instance) uses this to handle some locking back-off.

Signed-off-by: default avatarClément Léger <cleger@rivosinc.com>
Reviewed-by: default avatarAtish Patra <atishp@rivosinc.com>
Link: https://lore.kernel.org/r/20240221083108.1235311-1-cleger@rivosinc.com


Signed-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
parent 44138150

Documentation/arch/riscv/hwprobe.rst

+4 −0
Original line number Diff line number Diff line
@@ -188,6 +188,10 @@ The following keys are defined: 
       manual starting from commit 95cf1f9 ("Add changes requested by Ved

       during signoff")



  * :c:macro:`RISCV_HWPROBE_EXT_ZIHINTPAUSE`: The Zihintpause extension is

       supported as defined in the RISC-V ISA manual starting from commit

       d8ab5c78c207 ("Zihintpause is ratified").



* :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance

  information about the selected set of processors.

arch/riscv/include/uapi/asm/hwprobe.h

+1 −0
Original line number Diff line number Diff line
@@ -59,6 +59,7 @@ struct riscv_hwprobe { 
#define		RISCV_HWPROBE_EXT_ZTSO		(1ULL << 33)

#define		RISCV_HWPROBE_EXT_ZACAS		(1ULL << 34)

#define		RISCV_HWPROBE_EXT_ZICOND	(1ULL << 35)

#define		RISCV_HWPROBE_EXT_ZIHINTPAUSE	(1ULL << 36)

#define RISCV_HWPROBE_KEY_CPUPERF_0	5

#define		RISCV_HWPROBE_MISALIGNED_UNKNOWN	(0 << 0)

#define		RISCV_HWPROBE_MISALIGNED_EMULATED	(1 << 0)

arch/riscv/kernel/sys_hwprobe.c

+1 −0
Original line number Diff line number Diff line
@@ -111,6 +111,7 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair, 
		EXT_KEY(ZTSO);

		EXT_KEY(ZACAS);

		EXT_KEY(ZICOND);

		EXT_KEY(ZIHINTPAUSE);



		if (has_vector()) {

			EXT_KEY(ZVBB);