Commit 641b0c64 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux 

Pull clk updates from Stephen Boyd:
 "A pretty quiet cycle this time around. We have a bunch of new Qualcomm
  clk drivers, per usual, and then a handful of drivers for other SoCs.
  Then the usual pile of cleanups is fairly small data fixes or
  converting DT bindings to YAML so they can be validated.

  No changes to the core framework besides an OF node refcount bump that
  never got decremented.

  New Drivers:

   - 5L35023 variant of Versa 3 clock generator

   - Various Qualcomm clk controllers: IPQ CMN PLL, SM6115 LPASS, SM750
     global, tcsr, rpmh, and display. X Plus GPU and global. QCS615 rpmh
     and MSM8937 and MSM8940 RPM.

   - Qualcomm Pongo and Taycan Alpha PLLs

   - Qualcomm IPQ5424 NoC-related interconnect clks

   - Renesas RZ/G3E (R9A09G047) SoC clk driver

   - SAMA7D65 SoC clk driver

   - Samsung Exynos990 SoC clk driver"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (159 commits)
  clk: analogbits: Fix incorrect calculation of vco rate delta
  clk: bcm: rpi: Add disp clock
  clk: bcm: rpi: Create helper to retrieve private data
  clk: bcm: rpi: Enable minimize for all firmware clocks
  clk: bcm: rpi: Allow cpufreq driver to also adjust gpu clocks
  clk: bcm: rpi: Add ISP to exported clocks
  clk: stm32f4: support spread spectrum clock generation
  clk: stm32f4: use FIELD helpers to access the PLLCFGR fields
  dt-bindings: clock: st,stm32-rcc: support spread spectrum clocking
  dt-bindings: clock: convert stm32 rcc bindings to json-schema
  clk: Use str_enable_disable-like helpers
  clk: clk-loongson2: Fix the number count of clk provider
  clk: clk-loongson2: Switch to use devm_clk_hw_register_fixed_rate_parent_data()
  clk: starfive: Make _clk_get become a common helper function
  clk: en7523: Add clock for eMMC for EN7581
  dt-bindings: clock: add ID for eMMC for EN7581
  dt-bindings: clock: drop NUM_CLOCKS define for EN7581
  clk: en7523: Rework clock handling for different clock numbers
  clk: thead: Fix cpu2vp_clk for TH1520 AP_SUBSYS clocks
  clk: thead: Add CLK_IGNORE_UNUSED to fix TH1520 boot
  ...
parents abdebb28 53c9c276

Documentation/devicetree/bindings/clock/atmel,at91rm9200-pmc.yaml

+2 −0
Original line number Diff line number Diff line
@@ -43,6 +43,7 @@ properties: 
              - atmel,sama5d4-pmc

              - microchip,sam9x60-pmc

              - microchip,sam9x7-pmc

              - microchip,sama7d65-pmc

              - microchip,sama7g5-pmc

          - const: syscon
@@ -90,6 +91,7 @@ allOf: 
            enum:

              - microchip,sam9x60-pmc

              - microchip,sam9x7-pmc

              - microchip,sama7d65-pmc

              - microchip,sama7g5-pmc

    then:

      properties:

Documentation/devicetree/bindings/clock/atmel,at91sam9x5-sckc.yaml

+1 −0
Original line number Diff line number Diff line
@@ -20,6 +20,7 @@ properties: 
      - items:

          - enum:

              - microchip,sam9x7-sckc

              - microchip,sama7d65-sckc

              - microchip,sama7g5-sckc

          - const: microchip,sam9x60-sckc

Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml

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+77 −0
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/qcom,ipq9574-cmn-pll.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Qualcomm CMN PLL Clock Controller on IPQ SoC



maintainers:

  - Bjorn Andersson <andersson@kernel.org>

  - Luo Jie <quic_luoj@quicinc.com>



description:

  The CMN (or common) PLL clock controller expects a reference

  input clock. This reference clock is from the on-board Wi-Fi.

  The CMN PLL supplies a number of fixed rate output clocks to

  the devices providing networking functions and to GCC. These

  networking hardware include PPE (packet process engine), PCS

  and the externally connected switch or PHY devices. The CMN

  PLL block also outputs fixed rate clocks to GCC. The PLL's

  primary function is to enable fixed rate output clocks for

  networking hardware functions used with the IPQ SoC.



properties:

  compatible:

    enum:

      - qcom,ipq9574-cmn-pll



  reg:

    maxItems: 1



  clocks:

    items:

      - description: The reference clock. The supported clock rates include

          25000000, 31250000, 40000000, 48000000, 50000000 and 96000000 HZ.

      - description: The AHB clock

      - description: The SYS clock

    description:

      The reference clock is the source clock of CMN PLL, which is from the

      Wi-Fi. The AHB and SYS clocks must be enabled to access CMN PLL

      clock registers.



  clock-names:

    items:

      - const: ref

      - const: ahb

      - const: sys



  "#clock-cells":

    const: 1



required:

  - compatible

  - reg

  - clocks

  - clock-names

  - "#clock-cells"



additionalProperties: false



examples:

  - |

    #include <dt-bindings/clock/qcom,ipq-cmn-pll.h>

    #include <dt-bindings/clock/qcom,ipq9574-gcc.h>



    cmn_pll: clock-controller@9b000 {

        compatible = "qcom,ipq9574-cmn-pll";

        reg = <0x0009b000 0x800>;

        clocks = <&cmn_pll_ref_clk>,

                 <&gcc GCC_CMN_12GPLL_AHB_CLK>,

                 <&gcc GCC_CMN_12GPLL_SYS_CLK>;

        clock-names = "ref", "ahb", "sys";

        #clock-cells = <1>;

        assigned-clocks = <&cmn_pll CMN_PLL_CLK>;

        assigned-clock-rates-u64 = /bits/ 64 <12000000000>;

    };

...

Documentation/devicetree/bindings/clock/qcom,mmcc.yaml

+4 −0
Original line number Diff line number Diff line
@@ -78,6 +78,7 @@ allOf: 
    then:

      properties:

        clocks:

          minItems: 8

          items:

            - description: Board PXO source

            - description: PLL 3 clock
@@ -87,8 +88,10 @@ allOf: 
            - description: DSI phy instance 2 dsi clock

            - description: DSI phy instance 2 byte clock

            - description: HDMI phy PLL clock

            - description: LVDS PLL clock



        clock-names:

          minItems: 8

          items:

            - const: pxo

            - const: pll3
@@ -98,6 +101,7 @@ allOf: 
            - const: dsi2pll

            - const: dsi2pllbyte

            - const: hdmipll

            - const: lvdspll



  - if:

      properties:

Documentation/devicetree/bindings/clock/qcom,qcs615-gcc.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/qcom,qcs615-gcc.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Qualcomm Global Clock & Reset Controller on QCS615



maintainers:

  - Taniya Das <quic_tdas@quicinc.com>



description: |

  Qualcomm global clock control module provides the clocks, resets and power

  domains on QCS615.



  See also: include/dt-bindings/clock/qcom,qcs615-gcc.h



properties:

  compatible:

    const: qcom,qcs615-gcc



  clocks:

    items:

      - description: Board XO source

      - description: Board active XO source

      - description: Sleep clock source



  clock-names:

    items:

      - const: bi_tcxo

      - const: bi_tcxo_ao

      - const: sleep_clk



required:

  - compatible

  - clocks

  - clock-names

  - '#power-domain-cells'



allOf:

  - $ref: qcom,gcc.yaml#



unevaluatedProperties: false



examples:

  - |

    #include <dt-bindings/clock/qcom,rpmh.h>

    clock-controller@100000 {

      compatible = "qcom,qcs615-gcc";

      reg = <0x00100000 0x1f0000>;

      clocks = <&rpmhcc RPMH_CXO_CLK>,

               <&rpmhcc RPMH_CXO_CLK_A>,

               <&sleep_clk>;

      clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";

      #clock-cells = <1>;

      #reset-cells = <1>;

      #power-domain-cells = <1>;

    };

...