Commit 6428fcf2 authored by Keguang Zhang's avatar Keguang Zhang Committed by Thomas Bogendoerfer
Browse files

MIPS: dts: loongson: Add LS1B-DEMO board 



Add a device tree for LS1B-DEMO board, supporting CPU, clock, INTC,
UART, Ethernet, GPIO, USB host, RTC, watchdog, DMA, NAND, and AC97.

Signed-off-by: default avatarKeguang Zhang <keguang.zhang@gmail.com>
Signed-off-by: default avatarThomas Bogendoerfer <tsbogend@alpha.franken.de>
parent cfbb794c

MAINTAINERS

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@@ -17016,6 +17016,7 @@ M: Keguang Zhang <keguang.zhang@gmail.com> 
L:	linux-mips@vger.kernel.org

S:	Maintained

F:	Documentation/devicetree/bindings/*/loongson,ls1*.yaml

F:	arch/mips/boot/dts/loongson/loongson1*

F:	arch/mips/include/asm/mach-loongson32/

F:	arch/mips/loongson32/

F:	drivers/*/*loongson1*

arch/mips/boot/dts/Makefile

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@@ -8,6 +8,7 @@ subdir-$(CONFIG_FIT_IMAGE_FDT_BOSTON) += img 
subdir-$(CONFIG_MACH_INGENIC)		+= ingenic

subdir-$(CONFIG_LANTIQ)			+= lantiq

subdir-$(CONFIG_MACH_LOONGSON64)	+= loongson

subdir-$(CONFIG_MACH_LOONGSON32)	+= loongson

subdir-$(CONFIG_SOC_VCOREIII)		+= mscc

subdir-$(CONFIG_MIPS_MALTA)		+= mti

subdir-$(CONFIG_LEGACY_BOARD_SEAD3)	+= mti

arch/mips/boot/dts/loongson/Makefile

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@@ -5,3 +5,5 @@ dtb-$(CONFIG_MACH_LOONGSON64) += loongson64c_4core_rs780e.dtb 
dtb-$(CONFIG_MACH_LOONGSON64)	+= loongson64c_8core_rs780e.dtb

dtb-$(CONFIG_MACH_LOONGSON64)	+= loongson64g_4core_ls7a.dtb

dtb-$(CONFIG_MACH_LOONGSON64)	+= loongson64v_4core_virtio.dtb



dtb-$(CONFIG_MACH_LOONGSON32)	+= ls1b-demo.dtb

arch/mips/boot/dts/loongson/loongson1.dtsi

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// SPDX-License-Identifier: GPL-2.0

/*

 * Copyright (c) 2023-2025 Keguang Zhang <keguang.zhang@gmail.com>

 */



/dts-v1/;



#include <dt-bindings/clock/loongson,ls1x-clk.h>

#include <dt-bindings/interrupt-controller/irq.h>



/ {

	#address-cells = <1>;

	#size-cells = <1>;



	xtal: clock {

		compatible = "fixed-clock";

		clock-output-names = "xtal";

		#clock-cells = <0>;

	};



	cpus {

		#address-cells = <1>;

		#size-cells = <0>;



		cpu0: cpu@0 {

			reg = <0>;

			device_type = "cpu";

			clocks = <&clkc LS1X_CLKID_CPU>;

			#clock-cells = <1>;

		};

	};



	cpu_intc: interrupt-controller {

		compatible = "mti,cpu-interrupt-controller";

		interrupt-controller;

		#interrupt-cells = <1>;

		#address-cells = <0>;

	};



	soc: bus@1fd00000 {

		compatible = "simple-bus";

		#address-cells = <1>;

		#size-cells = <1>;

		ranges = <0x0 0x1fd00000 0x130000>;



		intc0: interrupt-controller@1040 {

			compatible = "loongson,ls1x-intc";

			reg = <0x1040 0x18>;

			interrupt-controller;

			interrupt-parent = <&cpu_intc>;

			interrupts = <2>;

			#interrupt-cells = <2>;

		};



		intc1: interrupt-controller@1058 {

			compatible = "loongson,ls1x-intc";

			reg = <0x1058 0x18>;

			interrupt-controller;

			interrupt-parent = <&cpu_intc>;

			interrupts = <3>;

			#interrupt-cells = <2>;

		};



		intc2: interrupt-controller@1070 {

			compatible = "loongson,ls1x-intc";

			reg = <0x1070 0x18>;

			interrupt-controller;

			interrupt-parent = <&cpu_intc>;

			interrupts = <4>;

			#interrupt-cells = <2>;

		};



		intc3: interrupt-controller@1088 {

			compatible = "loongson,ls1x-intc";

			reg = <0x1088 0x18>;

			interrupt-controller;

			interrupt-parent = <&cpu_intc>;

			interrupts = <5>;

			#interrupt-cells = <2>;

		};



		gpio0: gpio@10c0 {

			compatible = "loongson,ls1x-gpio";

			reg = <0x10c0 0x4>;

			gpio-controller;

			#gpio-cells = <2>;

		};



		gpio1: gpio@10c4 {

			compatible = "loongson,ls1x-gpio";

			reg = <0x10c4 0x4>;

			gpio-controller;

			#gpio-cells = <2>;

		};

	};



	apb: bus@1fe40000 {

		compatible = "simple-bus";

		#address-cells = <1>;

		#size-cells = <1>;

		ranges = <0x0 0x1fe40000 0xc0000>;



		uart0: serial@0 {

			compatible = "ns16550a";

			reg = <0x0 0x8>;

			clocks = <&clkc LS1X_CLKID_APB>;

			interrupt-parent = <&intc0>;

			interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;

			status = "disabled";

		};



		uart1: serial@4000 {

			compatible = "ns16550a";

			reg = <0x4000 0x8>;

			clocks = <&clkc LS1X_CLKID_APB>;

			interrupt-parent = <&intc0>;

			status = "disabled";

		};



		uart2: serial@8000 {

			compatible = "ns16550a";

			reg = <0x8000 0x8>;

			clocks = <&clkc LS1X_CLKID_APB>;

			interrupt-parent = <&intc0>;

			status = "disabled";

		};



		uart3: serial@c000 {

			compatible = "ns16550a";

			reg = <0xc000 0x8>;

			clocks = <&clkc LS1X_CLKID_APB>;

			interrupt-parent = <&intc0>;

			status = "disabled";

		};

	};

};

arch/mips/boot/dts/loongson/loongson1b.dtsi

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// SPDX-License-Identifier: GPL-2.0

/*

 * Copyright (c) 2023-2025 Keguang Zhang <keguang.zhang@gmail.com>

 */



/dts-v1/;

#include "loongson1.dtsi"



/ {

	cpu_opp_table: opp-table {

		compatible = "operating-points-v2";

		opp-shared;



		opp-44000000 {

			opp-hz = /bits/ 64 <44000000>;

		};

		opp-47142000 {

			opp-hz = /bits/ 64 <47142000>;

		};

		opp-50769000 {

			opp-hz = /bits/ 64 <50769000>;

		};

		opp-55000000 {

			opp-hz = /bits/ 64 <55000000>;

		};

		opp-60000000 {

			opp-hz = /bits/ 64 <60000000>;

		};

		opp-66000000 {

			opp-hz = /bits/ 64 <66000000>;

		};

		opp-73333000 {

			opp-hz = /bits/ 64 <73333000>;

		};

		opp-82500000 {

			opp-hz = /bits/ 64 <82500000>;

		};

		opp-94285000 {

			opp-hz = /bits/ 64 <94285000>;

		};

		opp-110000000 {

			opp-hz = /bits/ 64 <110000000>;

		};

		opp-132000000 {

			opp-hz = /bits/ 64 <132000000>;

		};

		opp-165000000 {

			opp-hz = /bits/ 64 <165000000>;

		};

		opp-220000000 {

			opp-hz = /bits/ 64 <220000000>;

		};

	};



	clkc: clock-controller@1fe78030 {

		compatible = "loongson,ls1b-clk";

		reg = <0x1fe78030 0x8>;

		clocks = <&xtal>;

		#clock-cells = <1>;

	};

};



&soc {

	syscon: syscon@420 {

		compatible = "loongson,ls1b-syscon", "syscon";

		reg = <0x420 0x8>;

	};



	dma: dma-controller@1160 {

		compatible = "loongson,ls1b-apbdma";

		reg = <0x1160 0x4>;

		interrupt-parent = <&intc0>;

		interrupts = <13 IRQ_TYPE_EDGE_RISING>,

			     <14 IRQ_TYPE_EDGE_RISING>,

			     <15 IRQ_TYPE_EDGE_RISING>;

		interrupt-names = "ch0", "ch1", "ch2";

		#dma-cells = <1>;

	};



	ehci: usb@100000 {

		compatible = "generic-ehci";

		reg = <0x100000 0x100>;

		interrupt-parent = <&intc1>;

		interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;

		status = "disabled";

	};



	ohci: usb@108000 {

		compatible = "generic-ohci";

		reg = <0x108000 0x100>;

		interrupt-parent = <&intc1>;

		interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;

		status = "disabled";

	};



	gmac0: ethernet@110000 {

		compatible = "loongson,ls1b-gmac", "snps,dwmac-3.50a";

		reg = <0x110000 0x10000>;

		clocks = <&clkc LS1X_CLKID_AHB>;

		clock-names = "stmmaceth";

		interrupt-parent = <&intc1>;

		interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "macirq";

		loongson,ls1-syscon = <&syscon>;

		snps,pbl = <1>;

		status = "disabled";

	};



	gmac1: ethernet@120000 {

		compatible = "loongson,ls1b-gmac", "snps,dwmac-3.50a";

		reg = <0x120000 0x10000>;

		clocks = <&clkc LS1X_CLKID_AHB>;

		clock-names = "stmmaceth";

		interrupt-parent = <&intc1>;

		interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "macirq";

		loongson,ls1-syscon = <&syscon>;

		snps,pbl = <1>;

		status = "disabled";

	};

};



&apb {

	clocksource: timer@1c030 {

		compatible = "loongson,ls1b-pwmtimer";

		reg = <0x1c030 0x10>;

		clocks = <&clkc LS1X_CLKID_APB>;

		interrupt-parent = <&intc0>;

		interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;

	};



	watchdog: watchdog@1c060 {

		compatible = "loongson,ls1b-wdt";

		reg = <0x1c060 0xc>;

		clocks = <&clkc LS1X_CLKID_APB>;

		status = "disabled";

	};



	rtc: rtc@24000 {

		compatible = "loongson,ls1b-rtc";

		reg = <0x24000 0x78>;

		interrupt-parent = <&intc0>;

		interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;

		status = "disabled";

	};



	ac97: audio-controller@34000 {

		compatible = "loongson,ls1b-ac97";

		reg = <0x34000 0x60>, <0x32420 0x4>, <0x34c4c 0x4>;

		reg-names = "ac97", "audio-tx", "audio-rx";

		dmas = <&dma 1>, <&dma 2>;

		dma-names = "tx", "rx";

		#sound-dai-cells = <0>;

		status = "disabled";

	};



	nand: nand-controller@38000 {

		compatible = "loongson,ls1b-nand-controller";

		reg = <0x38000 0x24>, <0x38040 0x4>;

		reg-names = "nand", "nand-dma";

		dmas = <&dma 0>;

		dma-names = "rxtx";

		#address-cells = <1>;

		#size-cells = <0>;

		status = "disabled";



		nand@0 {

			reg = <0>;

			label = "ls1x-nand";

			nand-use-soft-ecc-engine;

			nand-ecc-algo = "hamming";

		};

	};

};



&cpu0 {

	operating-points-v2 = <&cpu_opp_table>;

};



&gpio0 {

	ngpios = <31>;

};



&gpio1 {

	ngpios = <30>;

};



&uart1 {

	interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;

};



&uart2 {

	interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;

};



&uart3 {

	interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;

};