Commit 64314e3f authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/amdgpu: fix the PCIe lanes reporting in the INFO IOCTL 

Combine the platform and GPU caps like we do for PCIe Gen.
This aligns properly with expectations and documentation
for the interface.

Link: https://gitlab.freedesktop.org/drm/amd/-/issues/3820


Reviewed-by: default avatarYang Wang <kevinyang.wang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 757e8b95

drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c

+11 −8
Original line number Diff line number Diff line
@@ -846,7 +846,7 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) 
	case AMDGPU_INFO_DEV_INFO: {

		struct drm_amdgpu_info_device *dev_info;

		uint64_t vm_size;

		uint32_t pcie_gen_mask;

		uint32_t pcie_gen_mask, pcie_width_mask;



		dev_info = kzalloc(sizeof(*dev_info), GFP_KERNEL);

		if (!dev_info)
@@ -934,15 +934,18 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) 
		dev_info->tcc_disabled_mask = adev->gfx.config.tcc_disabled_mask;



		/* Combine the chip gen mask with the platform (CPU/mobo) mask. */

		pcie_gen_mask = adev->pm.pcie_gen_mask & (adev->pm.pcie_gen_mask >> 16);

		pcie_gen_mask = adev->pm.pcie_gen_mask &

			(adev->pm.pcie_gen_mask >> CAIL_PCIE_LINK_SPEED_SUPPORT_SHIFT);

		pcie_width_mask = adev->pm.pcie_mlw_mask &

			(adev->pm.pcie_mlw_mask >> CAIL_PCIE_LINK_WIDTH_SUPPORT_SHIFT);

		dev_info->pcie_gen = fls(pcie_gen_mask);

		dev_info->pcie_num_lanes =

			adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 ? 32 :

			adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 ? 16 :

			adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 ? 12 :

			adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 ? 8 :

			adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 ? 4 :

			adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 ? 2 : 1;

			pcie_width_mask & CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X32 ? 32 :

			pcie_width_mask & CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X16 ? 16 :

			pcie_width_mask & CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X12 ? 12 :

			pcie_width_mask & CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X8 ? 8 :

			pcie_width_mask & CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X4 ? 4 :

			pcie_width_mask & CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X2 ? 2 : 1;



		dev_info->tcp_cache_size = adev->gfx.config.gc_tcp_l1_size;

		dev_info->num_sqc_per_wgp = adev->gfx.config.gc_num_sqc_per_wgp;