Merge tag 'renesas-clk-for-v5.14-tag1' of... (6435c499) · Commits · git / linux-net

drivers/clk/renesas/clk-div6.c

+54 −26

Original line number	Diff line number	Diff line
		@@ -28,8 +28,7 @@
		* @hw: handle between common and hardware-specific interfaces
		* @reg: IO-remapped register
		* @div: divisor value (1-64)
		* @src_shift: Shift to access the register bits to select the parent clock
		* @src_width: Number of register bits to select the parent clock (may be 0)
		* @src_mask: Bitmask covering the register bits to select the parent clock
		* @nb: Notifier block to save/restore clock state for system resume
		* @parents: Array to map from valid parent clocks indices to hardware indices
		*/
		@@ -37,8 +36,7 @@ struct div6_clock {
		struct clk_hw hw;
		void __iomem *reg;
		unsigned int div;
		u32 src_shift;
		u32 src_width;
		u32 src_mask;
		struct notifier_block nb;
		u8 parents[];
		};
		@@ -99,15 +97,52 @@ static unsigned int cpg_div6_clock_calc_div(unsigned long rate,
		rate = 1;

		div = DIV_ROUND_CLOSEST(parent_rate, rate);
		return clamp_t(unsigned int, div, 1, 64);
		return clamp(div, 1U, 64U);
		}

		static long cpg_div6_clock_round_rate(struct clk_hw *hw, unsigned long rate,
		unsigned long *parent_rate)
		static int cpg_div6_clock_determine_rate(struct clk_hw *hw,
		struct clk_rate_request *req)
		{
		unsigned int div = cpg_div6_clock_calc_div(rate, *parent_rate);
		unsigned long prate, calc_rate, diff, best_rate, best_prate;
		unsigned int num_parents = clk_hw_get_num_parents(hw);
		struct clk_hw parent, best_parent = NULL;
		unsigned int i, min_div, max_div, div;
		unsigned long min_diff = ULONG_MAX;

		for (i = 0; i < num_parents; i++) {
		parent = clk_hw_get_parent_by_index(hw, i);
		if (!parent)
		continue;

		prate = clk_hw_get_rate(parent);
		if (!prate)
		continue;

		min_div = max(DIV_ROUND_UP(prate, req->max_rate), 1UL);
		max_div = req->min_rate ? min(prate / req->min_rate, 64UL) : 64;
		if (max_div < min_div)
		continue;

		div = cpg_div6_clock_calc_div(req->rate, prate);
		div = clamp(div, min_div, max_div);
		calc_rate = prate / div;
		diff = calc_rate > req->rate ? calc_rate - req->rate
		: req->rate - calc_rate;
		if (diff < min_diff) {
		best_rate = calc_rate;
		best_parent = parent;
		best_prate = prate;
		min_diff = diff;
		}
		}

		if (!best_parent)
		return -EINVAL;

		return *parent_rate / div;
		req->best_parent_rate = best_prate;
		req->best_parent_hw = best_parent;
		req->rate = best_rate;
		return 0;
		}

		static int cpg_div6_clock_set_rate(struct clk_hw *hw, unsigned long rate,
		@@ -133,11 +168,11 @@ static u8 cpg_div6_clock_get_parent(struct clk_hw *hw)
		unsigned int i;
		u8 hw_index;

		if (clock->src_width == 0)
		if (clock->src_mask == 0)
		return 0;

		hw_index = (readl(clock->reg) >> clock->src_shift) &
		(BIT(clock->src_width) - 1);
		hw_index = (readl(clock->reg) & clock->src_mask) >>
		__ffs(clock->src_mask);
		for (i = 0; i < clk_hw_get_num_parents(hw); i++) {
		if (clock->parents[i] == hw_index)
		return i;
		@@ -151,18 +186,13 @@ static u8 cpg_div6_clock_get_parent(struct clk_hw *hw)
		static int cpg_div6_clock_set_parent(struct clk_hw *hw, u8 index)
		{
		struct div6_clock *clock = to_div6_clock(hw);
		u8 hw_index;
		u32 mask;
		u32 src;

		if (index >= clk_hw_get_num_parents(hw))
		return -EINVAL;

		mask = ~((BIT(clock->src_width) - 1) << clock->src_shift);
		hw_index = clock->parents[index];

		writel((readl(clock->reg) & mask) \| (hw_index << clock->src_shift),
		clock->reg);

		src = clock->parents[index] << __ffs(clock->src_mask);
		writel((readl(clock->reg) & ~clock->src_mask) \| src, clock->reg);
		return 0;
		}

		@@ -173,7 +203,7 @@ static const struct clk_ops cpg_div6_clock_ops = {
		.get_parent = cpg_div6_clock_get_parent,
		.set_parent = cpg_div6_clock_set_parent,
		.recalc_rate = cpg_div6_clock_recalc_rate,
		.round_rate = cpg_div6_clock_round_rate,
		.determine_rate = cpg_div6_clock_determine_rate,
		.set_rate = cpg_div6_clock_set_rate,
		};

		@@ -236,17 +266,15 @@ struct clk * __init cpg_div6_register(const char *name,
		switch (num_parents) {
		case 1:
		/* fixed parent clock */
		clock->src_shift = clock->src_width = 0;
		clock->src_mask = 0;
		break;
		case 4:
		/* clock with EXSRC bits 6-7 */
		clock->src_shift = 6;
		clock->src_width = 2;
		clock->src_mask = GENMASK(7, 6);
		break;
		case 8:
		/* VCLK with EXSRC bits 12-14 */
		clock->src_shift = 12;
		clock->src_width = 3;
		clock->src_mask = GENMASK(14, 12);
		break;
		default:
		pr_err("%s: invalid number of parents for DIV6 clock %s\n",

drivers/clk/renesas/r8a77995-cpg-mssr.c

+1 −0

Original line number	Diff line number	Diff line
		@@ -75,6 +75,7 @@ static const struct cpg_core_clk r8a77995_core_clks[] __initconst = {
		DEF_RATE(".oco", CLK_OCO, 8 * 1000 * 1000),

		/* Core Clock Outputs */
		DEF_FIXED("za2", R8A77995_CLK_ZA2, CLK_PLL0D3, 2, 1),
		DEF_FIXED("z2", R8A77995_CLK_Z2, CLK_PLL0D3, 1, 1),
		DEF_FIXED("ztr", R8A77995_CLK_ZTR, CLK_PLL1, 6, 1),
		DEF_FIXED("zt", R8A77995_CLK_ZT, CLK_PLL1, 4, 1),

drivers/clk/renesas/r8a779a0-cpg-mssr.c

+4 −0

Original line number	Diff line number	Diff line
		@@ -180,6 +180,10 @@ static const struct mssr_mod_clk r8a779a0_mod_clks[] __initconst = {
		DEF_MOD("i2c4", 522, R8A779A0_CLK_S1D4),
		DEF_MOD("i2c5", 523, R8A779A0_CLK_S1D4),
		DEF_MOD("i2c6", 524, R8A779A0_CLK_S1D4),
		DEF_MOD("ispcs0", 612, R8A779A0_CLK_S1D1),
		DEF_MOD("ispcs1", 613, R8A779A0_CLK_S1D1),
		DEF_MOD("ispcs2", 614, R8A779A0_CLK_S1D1),
		DEF_MOD("ispcs3", 615, R8A779A0_CLK_S1D1),
		DEF_MOD("msi0", 618, R8A779A0_CLK_MSO),
		DEF_MOD("msi1", 619, R8A779A0_CLK_MSO),
		DEF_MOD("msi2", 620, R8A779A0_CLK_MSO),

drivers/clk/renesas/r9a06g032-clocks.c

+13 −12

Original line number	Diff line number	Diff line
		@@ -604,20 +604,19 @@ r9a06g032_div_clamp_div(struct r9a06g032_clk_div *clk,
		return div;
		}

		static long
		r9a06g032_div_round_rate(struct clk_hw *hw,
		unsigned long rate, unsigned long *prate)
		static int
		r9a06g032_div_determine_rate(struct clk_hw hw, struct clk_rate_request req)
		{
		struct r9a06g032_clk_div *clk = to_r9a06g032_div(hw);
		u32 div = DIV_ROUND_UP(*prate, rate);
		u32 div = DIV_ROUND_UP(req->best_parent_rate, req->rate);

		pr_devel("%s %pC %ld (prate %ld) (wanted div %u)\n", __func__,
		hw->clk, rate, *prate, div);
		hw->clk, req->rate, req->best_parent_rate, div);
		pr_devel(" min %d (%ld) max %d (%ld)\n",
		clk->min, DIV_ROUND_UP(*prate, clk->min),
		clk->max, DIV_ROUND_UP(*prate, clk->max));
		clk->min, DIV_ROUND_UP(req->best_parent_rate, clk->min),
		clk->max, DIV_ROUND_UP(req->best_parent_rate, clk->max));

		div = r9a06g032_div_clamp_div(clk, rate, *prate);
		div = r9a06g032_div_clamp_div(clk, req->rate, req->best_parent_rate);
		/*
		* this is a hack. Currently the serial driver asks for a clock rate
		* that is 16 times the baud rate -- and that is wildly outside the
		@@ -630,11 +629,13 @@ r9a06g032_div_round_rate(struct clk_hw *hw,
		if (clk->index == R9A06G032_DIV_UART \|\|
		clk->index == R9A06G032_DIV_P2_PG) {
		pr_devel("%s div uart hack!\n", __func__);
		return clk_get_rate(hw->clk);
		req->rate = clk_get_rate(hw->clk);
		return 0;
		}
		req->rate = DIV_ROUND_UP(req->best_parent_rate, div);
		pr_devel("%s %pC %ld / %u = %ld\n", __func__, hw->clk,
		prate, div, DIV_ROUND_UP(prate, div));
		return DIV_ROUND_UP(*prate, div);
		req->best_parent_rate, div, req->rate);
		return 0;
		}

		static int
		@@ -663,7 +664,7 @@ r9a06g032_div_set_rate(struct clk_hw *hw,

		static const struct clk_ops r9a06g032_clk_div_ops = {
		.recalc_rate = r9a06g032_div_recalc_rate,
		.round_rate = r9a06g032_div_round_rate,
		.determine_rate = r9a06g032_div_determine_rate,
		.set_rate = r9a06g032_div_set_rate,
		};

drivers/clk/renesas/rcar-gen3-cpg.c

+154 −29

Original line number	Diff line number	Diff line
		@@ -26,19 +26,135 @@
		#include "rcar-cpg-lib.h"
		#include "rcar-gen3-cpg.h"

		#define CPG_PLL0CR 0x00d8
		#define CPG_PLLECR 0x00d0 /* PLL Enable Control Register */

		#define CPG_PLLECR_PLLST(n) BIT(8 + (n)) /* PLLn Circuit Status */

		#define CPG_PLL0CR 0x00d8 /* PLLn Control Registers */
		#define CPG_PLL2CR 0x002c
		#define CPG_PLL4CR 0x01f4

		#define CPG_PLLnCR_STC_MASK GENMASK(30, 24) /* PLL Circuit Mult. Ratio */

		#define CPG_RCKCR_CKSEL BIT(15) /* RCLK Clock Source Select */

		/* PLL Clocks */
		struct cpg_pll_clk {
		struct clk_hw hw;
		void __iomem *pllcr_reg;
		void __iomem *pllecr_reg;
		unsigned int fixed_mult;
		u32 pllecr_pllst_mask;
		};

		#define to_pll_clk(_hw) container_of(_hw, struct cpg_pll_clk, hw)

		static unsigned long cpg_pll_clk_recalc_rate(struct clk_hw *hw,
		unsigned long parent_rate)
		{
		struct cpg_pll_clk *pll_clk = to_pll_clk(hw);
		unsigned int mult;
		u32 val;

		val = readl(pll_clk->pllcr_reg) & CPG_PLLnCR_STC_MASK;
		mult = (val >> __ffs(CPG_PLLnCR_STC_MASK)) + 1;

		return parent_rate * mult * pll_clk->fixed_mult;
		}

		static int cpg_pll_clk_determine_rate(struct clk_hw *hw,
		struct clk_rate_request *req)
		{
		struct cpg_pll_clk *pll_clk = to_pll_clk(hw);
		unsigned int min_mult, max_mult, mult;
		unsigned long prate;

		prate = req->best_parent_rate * pll_clk->fixed_mult;
		min_mult = max(div64_ul(req->min_rate, prate), 1ULL);
		max_mult = min(div64_ul(req->max_rate, prate), 128ULL);
		if (max_mult < min_mult)
		return -EINVAL;

		mult = DIV_ROUND_CLOSEST_ULL(req->rate, prate);
		mult = clamp(mult, min_mult, max_mult);

		req->rate = prate * mult;
		return 0;
		}

		static int cpg_pll_clk_set_rate(struct clk_hw *hw, unsigned long rate,
		unsigned long parent_rate)
		{
		struct cpg_pll_clk *pll_clk = to_pll_clk(hw);
		unsigned int mult, i;
		u32 val;

		mult = DIV_ROUND_CLOSEST_ULL(rate, parent_rate * pll_clk->fixed_mult);
		mult = clamp(mult, 1U, 128U);

		val = readl(pll_clk->pllcr_reg);
		val &= ~CPG_PLLnCR_STC_MASK;
		val \|= (mult - 1) << __ffs(CPG_PLLnCR_STC_MASK);
		writel(val, pll_clk->pllcr_reg);

		for (i = 1000; i; i--) {
		if (readl(pll_clk->pllecr_reg) & pll_clk->pllecr_pllst_mask)
		return 0;

		cpu_relax();
		}

		return -ETIMEDOUT;
		}

		static const struct clk_ops cpg_pll_clk_ops = {
		.recalc_rate = cpg_pll_clk_recalc_rate,
		.determine_rate = cpg_pll_clk_determine_rate,
		.set_rate = cpg_pll_clk_set_rate,
		};

		static struct clk * __init cpg_pll_clk_register(const char *name,
		const char *parent_name,
		void __iomem *base,
		unsigned int mult,
		unsigned int offset,
		unsigned int index)

		{
		struct cpg_pll_clk *pll_clk;
		struct clk_init_data init = {};
		struct clk *clk;

		pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL);
		if (!pll_clk)
		return ERR_PTR(-ENOMEM);

		init.name = name;
		init.ops = &cpg_pll_clk_ops;
		init.parent_names = &parent_name;
		init.num_parents = 1;

		pll_clk->hw.init = &init;
		pll_clk->pllcr_reg = base + offset;
		pll_clk->pllecr_reg = base + CPG_PLLECR;
		pll_clk->fixed_mult = mult; /* PLL refclk x (setting + 1) x mult */
		pll_clk->pllecr_pllst_mask = CPG_PLLECR_PLLST(index);

		clk = clk_register(NULL, &pll_clk->hw);
		if (IS_ERR(clk))
		kfree(pll_clk);

		return clk;
		}

		/*
		* Z Clock & Z2 Clock
		*
		* Traits of this clock:
		* prepare - clk_prepare only ensures that parents are prepared
		* enable - clk_enable only ensures that parents are enabled
		* rate - rate is adjustable. clk->rate = (parent->rate * mult / 32 ) / 2
		* rate - rate is adjustable.
		* clk->rate = (parent->rate * mult / 32 ) / fixed_div
		* parent - fixed parent. No clk_set_parent support
		*/
		#define CPG_FRQCRB 0x00000004
		@@ -49,8 +165,9 @@ struct cpg_z_clk {
		struct clk_hw hw;
		void __iomem *reg;
		void __iomem *kick_reg;
		unsigned long mask;
		unsigned long max_rate; /* Maximum rate for normal mode */
		unsigned int fixed_div;
		u32 mask;
		};

		#define to_z_clk(_hw) container_of(_hw, struct cpg_z_clk, hw)
		@@ -74,7 +191,18 @@ static int cpg_z_clk_determine_rate(struct clk_hw *hw,
		{
		struct cpg_z_clk *zclk = to_z_clk(hw);
		unsigned int min_mult, max_mult, mult;
		unsigned long prate;
		unsigned long rate, prate;

		rate = min(req->rate, req->max_rate);
		if (rate <= zclk->max_rate) {
		/* Set parent rate to initial value for normal modes */
		prate = zclk->max_rate;
		} else {
		/* Set increased parent rate for boost modes */
		prate = rate;
		}
		req->best_parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw),
		prate * zclk->fixed_div);

		prate = req->best_parent_rate / zclk->fixed_div;
		min_mult = max(div64_ul(req->min_rate * 32ULL, prate), 1ULL);
		@@ -82,10 +210,10 @@ static int cpg_z_clk_determine_rate(struct clk_hw *hw,
		if (max_mult < min_mult)
		return -EINVAL;

		mult = div64_ul(req->rate * 32ULL, prate);
		mult = DIV_ROUND_CLOSEST_ULL(rate * 32ULL, prate);
		mult = clamp(mult, min_mult, max_mult);

		req->rate = div_u64((u64)prate * mult, 32);
		req->rate = DIV_ROUND_CLOSEST_ULL((u64)prate * mult, 32);
		return 0;
		}

		@@ -103,8 +231,7 @@ static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate,
		if (readl(zclk->kick_reg) & CPG_FRQCRB_KICK)
		return -EBUSY;

		cpg_reg_modify(zclk->reg, zclk->mask,
		((32 - mult) << __ffs(zclk->mask)) & zclk->mask);
		cpg_reg_modify(zclk->reg, zclk->mask, (32 - mult) << __ffs(zclk->mask));

		/*
		* Set KICK bit in FRQCRB to update hardware setting and wait for
		@@ -117,7 +244,7 @@ static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate,
		*
		* Using experimental measurements, it seems that no more than
		* ~10 iterations are needed, independently of the CPU rate.
		* Since this value might be dependent of external xtal rate, pll1
		* Since this value might be dependent on external xtal rate, pll1
		* rate or even the other emulation clocks rate, use 1000 as a
		* "super" safe value.
		*/
		@@ -153,7 +280,7 @@ static struct clk * __init cpg_z_clk_register(const char *name,

		init.name = name;
		init.ops = &cpg_z_clk_ops;
		init.flags = 0;
		init.flags = CLK_SET_RATE_PARENT;
		init.parent_names = &parent_name;
		init.num_parents = 1;

		@@ -164,9 +291,13 @@ static struct clk * __init cpg_z_clk_register(const char *name,
		zclk->fixed_div = div; /* PLLVCO x 1/div x SYS-CPU divider */

		clk = clk_register(NULL, &zclk->hw);
		if (IS_ERR(clk))
		if (IS_ERR(clk)) {
		kfree(zclk);
		return clk;
		}

		zclk->max_rate = clk_hw_get_rate(clk_hw_get_parent(&zclk->hw)) /
		zclk->fixed_div;
		return clk;
		}

		@@ -314,16 +445,13 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev,

		case CLK_TYPE_GEN3_PLL0:
		/*
		* PLL0 is a configurable multiplier clock. Register it as a
		* fixed factor clock for now as there's no generic multiplier
		* clock implementation and we currently have no need to change
		* the multiplier value.
		* PLL0 is implemented as a custom clock, to change the
		* multiplier when cpufreq changes between normal and boost
		* modes.
		*/
		value = readl(base + CPG_PLL0CR);
		mult = (((value >> 24) & 0x7f) + 1) * 2;
		if (cpg_quirks & PLL_ERRATA)
		mult *= 2;
		break;
		mult = (cpg_quirks & PLL_ERRATA) ? 4 : 2;
		return cpg_pll_clk_register(core->name, __clk_get_name(parent),
		base, mult, CPG_PLL0CR, 0);

		case CLK_TYPE_GEN3_PLL1:
		mult = cpg_pll_config->pll1_mult;
		@@ -332,16 +460,13 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev,

		case CLK_TYPE_GEN3_PLL2:
		/*
		* PLL2 is a configurable multiplier clock. Register it as a
		* fixed factor clock for now as there's no generic multiplier
		* clock implementation and we currently have no need to change
		* the multiplier value.
		* PLL2 is implemented as a custom clock, to change the
		* multiplier when cpufreq changes between normal and boost
		* modes.
		*/
		value = readl(base + CPG_PLL2CR);
		mult = (((value >> 24) & 0x7f) + 1) * 2;
		if (cpg_quirks & PLL_ERRATA)
		mult *= 2;
		break;
		mult = (cpg_quirks & PLL_ERRATA) ? 4 : 2;
		return cpg_pll_clk_register(core->name, __clk_get_name(parent),
		base, mult, CPG_PLL2CR, 2);

		case CLK_TYPE_GEN3_PLL3:
		mult = cpg_pll_config->pll3_mult;