Commit 647b93f6 authored by Pu Lehui's avatar Pu Lehui Committed by Daniel Borkmann
Browse files

riscv, bpf: Add necessary Zbb instructions 



Add necessary Zbb instructions introduced by [0] to reduce code size and
improve performance of RV64 JIT. Meanwhile, a runtime deteted helper is
added to check whether the CPU supports Zbb instructions.

Signed-off-by: default avatarPu Lehui <pulehui@huawei.com>
Signed-off-by: default avatarDaniel Borkmann <daniel@iogearbox.net>
Tested-by: default avatarBjörn Töpel <bjorn@rivosinc.com>
Acked-by: default avatarBjörn Töpel <bjorn@kernel.org>
Link: https://github.com/riscv/riscv-bitmanip/releases/download/1.0.0/bitmanip-1.0.0-38-g865e7a7.pdf [0]
Link: https://lore.kernel.org/bpf/20240115131235.2914289-5-pulehui@huaweicloud.com
parent 361db44c

arch/riscv/net/bpf_jit.h

+32 −0
Original line number Diff line number Diff line
@@ -18,6 +18,11 @@ static inline bool rvc_enabled(void) 
	return IS_ENABLED(CONFIG_RISCV_ISA_C);

}



static inline bool rvzbb_enabled(void)

{

	return IS_ENABLED(CONFIG_RISCV_ISA_ZBB) && riscv_has_extension_likely(RISCV_ISA_EXT_ZBB);

}



enum {

	RV_REG_ZERO =	0,	/* The constant value 0 */

	RV_REG_RA =	1,	/* Return address */
@@ -730,6 +735,33 @@ static inline u16 rvc_swsp(u32 imm8, u8 rs2) 
	return rv_css_insn(0x6, imm, rs2, 0x2);

}



/* RVZBB instrutions. */

static inline u32 rvzbb_sextb(u8 rd, u8 rs1)

{

	return rv_i_insn(0x604, rs1, 1, rd, 0x13);

}



static inline u32 rvzbb_sexth(u8 rd, u8 rs1)

{

	return rv_i_insn(0x605, rs1, 1, rd, 0x13);

}



static inline u32 rvzbb_zexth(u8 rd, u8 rs)

{

	if (IS_ENABLED(CONFIG_64BIT))

		return rv_i_insn(0x80, rs, 4, rd, 0x3b);



	return rv_i_insn(0x80, rs, 4, rd, 0x33);

}



static inline u32 rvzbb_rev8(u8 rd, u8 rs)

{

	if (IS_ENABLED(CONFIG_64BIT))

		return rv_i_insn(0x6b8, rs, 5, rd, 0x13);



	return rv_i_insn(0x698, rs, 5, rd, 0x13);

}



/*

 * RV64-only instructions.

 *