Commit 64b2a6a0 authored by Tejas Upadhyay's avatar Tejas Upadhyay Committed by Rodrigo Vivi
Browse files

drm/i915/gt: use get_reset_domain() helper 



We dont need to implement reset_domain in intel_engine
_setup(), but can be done as a helper. Implemented as
engine->reset_domain = get_reset_domain().

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: default avatarTejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
Reviewed-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220217123223.748184-1-tejaskumarx.surendrakumar.upadhyay@intel.com
parent 4b31b8e3

drivers/gpu/drm/i915/gt/intel_engine_cs.c

+42 −32
Original line number Diff line number Diff line
@@ -290,6 +290,46 @@ static void nop_irq_handler(struct intel_engine_cs *engine, u16 iir) 
	GEM_DEBUG_WARN_ON(iir);

}



static u32 get_reset_domain(u8 ver, enum intel_engine_id id)

{

	u32 reset_domain;



	if (ver >= 11) {

		static const u32 engine_reset_domains[] = {

			[RCS0]  = GEN11_GRDOM_RENDER,

			[BCS0]  = GEN11_GRDOM_BLT,

			[VCS0]  = GEN11_GRDOM_MEDIA,

			[VCS1]  = GEN11_GRDOM_MEDIA2,

			[VCS2]  = GEN11_GRDOM_MEDIA3,

			[VCS3]  = GEN11_GRDOM_MEDIA4,

			[VCS4]  = GEN11_GRDOM_MEDIA5,

			[VCS5]  = GEN11_GRDOM_MEDIA6,

			[VCS6]  = GEN11_GRDOM_MEDIA7,

			[VCS7]  = GEN11_GRDOM_MEDIA8,

			[VECS0] = GEN11_GRDOM_VECS,

			[VECS1] = GEN11_GRDOM_VECS2,

			[VECS2] = GEN11_GRDOM_VECS3,

			[VECS3] = GEN11_GRDOM_VECS4,

		};

		GEM_BUG_ON(id >= ARRAY_SIZE(engine_reset_domains) ||

			   !engine_reset_domains[id]);

		reset_domain = engine_reset_domains[id];

	} else {

		static const u32 engine_reset_domains[] = {

			[RCS0]  = GEN6_GRDOM_RENDER,

			[BCS0]  = GEN6_GRDOM_BLT,

			[VCS0]  = GEN6_GRDOM_MEDIA,

			[VCS1]  = GEN8_GRDOM_MEDIA2,

			[VECS0] = GEN6_GRDOM_VECS,

		};

		GEM_BUG_ON(id >= ARRAY_SIZE(engine_reset_domains) ||

			   !engine_reset_domains[id]);

		reset_domain = engine_reset_domains[id];

	}



	return reset_domain;

}



static int intel_engine_setup(struct intel_gt *gt, enum intel_engine_id id,

			      u8 logical_instance)

{
@@ -325,38 +365,8 @@ static int intel_engine_setup(struct intel_gt *gt, enum intel_engine_id id, 
	engine->id = id;

	engine->legacy_idx = INVALID_ENGINE;

	engine->mask = BIT(id);

	if (GRAPHICS_VER(gt->i915) >= 11) {

		static const u32 engine_reset_domains[] = {

			[RCS0]  = GEN11_GRDOM_RENDER,

			[BCS0]  = GEN11_GRDOM_BLT,

			[VCS0]  = GEN11_GRDOM_MEDIA,

			[VCS1]  = GEN11_GRDOM_MEDIA2,

			[VCS2]  = GEN11_GRDOM_MEDIA3,

			[VCS3]  = GEN11_GRDOM_MEDIA4,

			[VCS4]  = GEN11_GRDOM_MEDIA5,

			[VCS5]  = GEN11_GRDOM_MEDIA6,

			[VCS6]  = GEN11_GRDOM_MEDIA7,

			[VCS7]  = GEN11_GRDOM_MEDIA8,

			[VECS0] = GEN11_GRDOM_VECS,

			[VECS1] = GEN11_GRDOM_VECS2,

			[VECS2] = GEN11_GRDOM_VECS3,

			[VECS3] = GEN11_GRDOM_VECS4,

		};

		GEM_BUG_ON(id >= ARRAY_SIZE(engine_reset_domains) ||

			   !engine_reset_domains[id]);

		engine->reset_domain = engine_reset_domains[id];

	} else {

		static const u32 engine_reset_domains[] = {

			[RCS0]  = GEN6_GRDOM_RENDER,

			[BCS0]  = GEN6_GRDOM_BLT,

			[VCS0]  = GEN6_GRDOM_MEDIA,

			[VCS1]  = GEN8_GRDOM_MEDIA2,

			[VECS0] = GEN6_GRDOM_VECS,

		};

		GEM_BUG_ON(id >= ARRAY_SIZE(engine_reset_domains) ||

			   !engine_reset_domains[id]);

		engine->reset_domain = engine_reset_domains[id];

	}

	engine->reset_domain = get_reset_domain(GRAPHICS_VER(gt->i915),

						id);

	engine->i915 = i915;

	engine->gt = gt;

	engine->uncore = gt->uncore;