Commit 64bceed3 authored by Yunfei Dong's avatar Yunfei Dong Committed by Matthias Brugger
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arm64: dts: mt8195: Add video decoder node 



Add video decoder node to mt8195 device tree.

Signed-off-by: default avatarYunfei Dong <yunfei.dong@mediatek.com>
Signed-off-by: default avatarAllen-KH Cheng <allen-kh.cheng@mediatek.com>
Reviewed-by: default avatarAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: default avatarChen-Yu Tsai <wenst@chromium.org>
Tested-by: default avatarChen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20230303013842.23259-7-allen-kh.cheng@mediatek.com


Signed-off-by: default avatarMatthias Brugger <matthias.bgg@gmail.com>
parent 1b85a425

arch/arm64/boot/dts/mediatek/mt8195.dtsi

+70 −0
Original line number Diff line number Diff line
@@ -2370,6 +2370,76 @@ larb18: larb@17201000 { 
			power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;

		};



		video-codec@18000000 {

			compatible = "mediatek,mt8195-vcodec-dec";

			mediatek,scp = <&scp>;

			iommus = <&iommu_vdo M4U_PORT_L21_VDEC_MC_EXT>;

			#address-cells = <2>;

			#size-cells = <2>;

			reg = <0 0x18000000 0 0x1000>,

			      <0 0x18004000 0 0x1000>;

			ranges = <0 0 0 0x18000000 0 0x26000>;



			video-codec@2000 {

				compatible = "mediatek,mtk-vcodec-lat-soc";

				reg = <0 0x2000 0 0x800>;

				iommus = <&iommu_vpp M4U_PORT_L23_VDEC_UFO_ENC_EXT>,

					 <&iommu_vpp M4U_PORT_L23_VDEC_RDMA_EXT>;

				clocks = <&topckgen CLK_TOP_VDEC>,

					 <&vdecsys_soc CLK_VDEC_SOC_VDEC>,

					 <&vdecsys_soc CLK_VDEC_SOC_LAT>,

					 <&topckgen CLK_TOP_UNIVPLL_D4>;

				clock-names = "sel", "vdec", "lat", "top";

				assigned-clocks = <&topckgen CLK_TOP_VDEC>;

				assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;

				power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;

			};



			video-codec@10000 {

				compatible = "mediatek,mtk-vcodec-lat";

				reg = <0 0x10000 0 0x800>;

				interrupts = <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH 0>;

				iommus = <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_VLD_EXT>,

					 <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_VLD2_EXT>,

					 <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_AVC_MC_EXT>,

					 <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_PRED_RD_EXT>,

					 <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_TILE_EXT>,

					 <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_WDMA_EXT>;

				clocks = <&topckgen CLK_TOP_VDEC>,

					 <&vdecsys_soc CLK_VDEC_SOC_VDEC>,

					 <&vdecsys_soc CLK_VDEC_SOC_LAT>,

					 <&topckgen CLK_TOP_UNIVPLL_D4>;

				clock-names = "sel", "vdec", "lat", "top";

				assigned-clocks = <&topckgen CLK_TOP_VDEC>;

				assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;

				power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;

			};



			video-codec@25000 {

				compatible = "mediatek,mtk-vcodec-core";

				reg = <0 0x25000 0 0x1000>;		/* VDEC_CORE_MISC */

				interrupts = <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH 0>;

				iommus = <&iommu_vdo M4U_PORT_L21_VDEC_MC_EXT>,

					 <&iommu_vdo M4U_PORT_L21_VDEC_UFO_EXT>,

					 <&iommu_vdo M4U_PORT_L21_VDEC_PP_EXT>,

					 <&iommu_vdo M4U_PORT_L21_VDEC_PRED_RD_EXT>,

					 <&iommu_vdo M4U_PORT_L21_VDEC_PRED_WR_EXT>,

					 <&iommu_vdo M4U_PORT_L21_VDEC_PPWRAP_EXT>,

					 <&iommu_vdo M4U_PORT_L21_VDEC_TILE_EXT>,

					 <&iommu_vdo M4U_PORT_L21_VDEC_VLD_EXT>,

					 <&iommu_vdo M4U_PORT_L21_VDEC_VLD2_EXT>,

					 <&iommu_vdo M4U_PORT_L21_VDEC_AVC_MV_EXT>;

				clocks = <&topckgen CLK_TOP_VDEC>,

					 <&vdecsys CLK_VDEC_VDEC>,

					 <&vdecsys CLK_VDEC_LAT>,

					 <&topckgen CLK_TOP_UNIVPLL_D4>;

				clock-names = "sel", "vdec", "lat", "top";

				assigned-clocks = <&topckgen CLK_TOP_VDEC>;

				assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;

				power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>;

			};

		};



		larb24: larb@1800d000 {

			compatible = "mediatek,mt8195-smi-larb";

			reg = <0 0x1800d000 0 0x1000>;