Commit 64f7b81f authored by Kuogee Hsieh's avatar Kuogee Hsieh Committed by Dmitry Baryshkov
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drm/msm/dpu: add support of new peripheral flush mechanism 



Introduce a peripheral flushing mechanism to decouple peripheral
metadata flushing from timing engine related flush.

Changes in v2:
	- Fixed some misalignment issues

Signed-off-by: default avatarKuogee Hsieh <quic_khsieh@quicinc.com>
Signed-off-by: default avatarPaloma Arellano <quic_parellan@quicinc.com>
Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/579619/
Link: https://lore.kernel.org/r/20240222194025.25329-15-quic_parellan@quicinc.com


Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
parent 55fb8ffc

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c

+17 −0
Original line number Diff line number Diff line
@@ -39,6 +39,7 @@ 
#define   CTL_WB_FLUSH                  0x108

#define   CTL_INTF_FLUSH                0x110

#define   CTL_CDM_FLUSH                0x114

#define   CTL_PERIPH_FLUSH              0x128

#define   CTL_INTF_MASTER               0x134

#define   CTL_DSPP_n_FLUSH(n)           ((0x13C) + ((n) * 4))
@@ -49,6 +50,7 @@ 
#define  MERGE_3D_IDX   23

#define  DSC_IDX        22

#define CDM_IDX         26

#define  PERIPH_IDX     30

#define  INTF_IDX       31

#define WB_IDX          16

#define  DSPP_IDX       29  /* From DPU hw rev 7.x.x */
@@ -151,6 +153,10 @@ static inline void dpu_hw_ctl_trigger_flush_v1(struct dpu_hw_ctl *ctx) 
				ctx->pending_dspp_flush_mask[dspp - DSPP_0]);

		}



	if (ctx->pending_flush_mask & BIT(PERIPH_IDX))

		DPU_REG_WRITE(&ctx->hw, CTL_PERIPH_FLUSH,

			      ctx->pending_periph_flush_mask);



	if (ctx->pending_flush_mask & BIT(DSC_IDX))

		DPU_REG_WRITE(&ctx->hw, CTL_DSC_FLUSH,

			      ctx->pending_dsc_flush_mask);
@@ -311,6 +317,13 @@ static void dpu_hw_ctl_update_pending_flush_intf_v1(struct dpu_hw_ctl *ctx, 
	ctx->pending_flush_mask |= BIT(INTF_IDX);

}



static void dpu_hw_ctl_update_pending_flush_periph_v1(struct dpu_hw_ctl *ctx,

						      enum dpu_intf intf)

{

	ctx->pending_periph_flush_mask |= BIT(intf - INTF_0);

	ctx->pending_flush_mask |= BIT(PERIPH_IDX);

}



static void dpu_hw_ctl_update_pending_flush_merge_3d_v1(struct dpu_hw_ctl *ctx,

		enum dpu_merge_3d merge_3d)

{
@@ -680,6 +693,10 @@ static void _setup_ctl_ops(struct dpu_hw_ctl_ops *ops, 
		ops->reset_intf_cfg = dpu_hw_ctl_reset_intf_cfg_v1;

		ops->update_pending_flush_intf =

			dpu_hw_ctl_update_pending_flush_intf_v1;



		ops->update_pending_flush_periph =

			dpu_hw_ctl_update_pending_flush_periph_v1;



		ops->update_pending_flush_merge_3d =

			dpu_hw_ctl_update_pending_flush_merge_3d_v1;

		ops->update_pending_flush_wb = dpu_hw_ctl_update_pending_flush_wb_v1;

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h

+10 −0
Original line number Diff line number Diff line
@@ -122,6 +122,15 @@ struct dpu_hw_ctl_ops { 
	void (*update_pending_flush_intf)(struct dpu_hw_ctl *ctx,

		enum dpu_intf blk);



	/**

	 * OR in the given flushbits to the cached pending_(periph_)flush_mask

	 * No effect on hardware

	 * @ctx       : ctl path ctx pointer

	 * @blk       : interface block index

	 */

	void (*update_pending_flush_periph)(struct dpu_hw_ctl *ctx,

					    enum dpu_intf blk);



	/**

	 * OR in the given flushbits to the cached pending_(merge_3d_)flush_mask

	 * No effect on hardware
@@ -264,6 +273,7 @@ struct dpu_hw_ctl { 
	u32 pending_flush_mask;

	u32 pending_intf_flush_mask;

	u32 pending_wb_flush_mask;

	u32 pending_periph_flush_mask;

	u32 pending_merge_3d_flush_mask;

	u32 pending_dspp_flush_mask[DSPP_MAX - DSPP_0];

	u32 pending_dsc_flush_mask;