Commit 64f8e73d authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'x86-splitlock-2021-04-26' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull x86 bus lock detection updates from Thomas Gleixner:
 "Support for enhanced split lock detection:

  Newer CPUs provide a second mechanism to detect operations with lock
  prefix which go accross a cache line boundary. Such operations have to
  take bus lock which causes a system wide performance degradation when
  these operations happen frequently.

  The new mechanism is not using the #AC exception. It triggers #DB and
  is restricted to operations in user space. Kernel side split lock
  access can only be detected by the #AC based variant.

  Contrary to the #AC based mechanism the #DB based variant triggers
  _after_ the instruction was executed. The mechanism is CPUID
  enumerated and contrary to the #AC version which is based on the magic
  TEST_CTRL_MSR and model/family based enumeration on the way to become
  architectural"

* tag 'x86-splitlock-2021-04-26' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  Documentation/admin-guide: Change doc for split_lock_detect parameter
  x86/traps: Handle #DB for bus lock
  x86/cpufeatures: Enumerate #DB for bus lock detection
parents eea2647e ebca1770

Documentation/admin-guide/kernel-parameters.txt

+16 −6
Original line number Diff line number Diff line
@@ -5111,27 +5111,37 @@ 
	spia_peddr=



	split_lock_detect=

			[X86] Enable split lock detection

			[X86] Enable split lock detection or bus lock detection



			When enabled (and if hardware support is present), atomic

			instructions that access data across cache line

			boundaries will result in an alignment check exception.

			boundaries will result in an alignment check exception

			for split lock detection or a debug exception for

			bus lock detection.



			off	- not enabled



			warn	- the kernel will emit rate limited warnings

			warn	- the kernel will emit rate-limited warnings

				  about applications triggering the #AC

				  exception. This mode is the default on CPUs

				  that supports split lock detection.

				  exception or the #DB exception. This mode is

				  the default on CPUs that support split lock

				  detection or bus lock detection. Default

				  behavior is by #AC if both features are

				  enabled in hardware.



			fatal	- the kernel will send SIGBUS to applications

				  that trigger the #AC exception.

				  that trigger the #AC exception or the #DB

				  exception. Default behavior is by #AC if

				  both features are enabled in hardware.



			If an #AC exception is hit in the kernel or in

			firmware (i.e. not while executing in user mode)

			the kernel will oops in either "warn" or "fatal"

			mode.



			#DB exception for bus lock is triggered only when

			CPL > 0.



	srbds=		[X86,INTEL]

			Control the Special Register Buffer Data Sampling

			(SRBDS) mitigation.

arch/x86/include/asm/cpu.h

+5 −2
Original line number Diff line number Diff line
@@ -41,12 +41,13 @@ unsigned int x86_family(unsigned int sig); 
unsigned int x86_model(unsigned int sig);

unsigned int x86_stepping(unsigned int sig);

#ifdef CONFIG_CPU_SUP_INTEL

extern void __init cpu_set_core_cap_bits(struct cpuinfo_x86 *c);

extern void __init sld_setup(struct cpuinfo_x86 *c);

extern void switch_to_sld(unsigned long tifn);

extern bool handle_user_split_lock(struct pt_regs *regs, long error_code);

extern bool handle_guest_split_lock(unsigned long ip);

extern void handle_bus_lock(struct pt_regs *regs);

#else

static inline void __init cpu_set_core_cap_bits(struct cpuinfo_x86 *c) {}

static inline void __init sld_setup(struct cpuinfo_x86 *c) {}

static inline void switch_to_sld(unsigned long tifn) {}

static inline bool handle_user_split_lock(struct pt_regs *regs, long error_code)

{
@@ -57,6 +58,8 @@ static inline bool handle_guest_split_lock(unsigned long ip) 
{

	return false;

}



static inline void handle_bus_lock(struct pt_regs *regs) {}

#endif

#ifdef CONFIG_IA32_FEAT_CTL

void init_ia32_feat_ctl(struct cpuinfo_x86 *c);

arch/x86/include/asm/cpufeatures.h

+1 −0
Original line number Diff line number Diff line
@@ -358,6 +358,7 @@ 
#define X86_FEATURE_AVX512_VPOPCNTDQ	(16*32+14) /* POPCNT for vectors of DW/QW */

#define X86_FEATURE_LA57		(16*32+16) /* 5-level page tables */

#define X86_FEATURE_RDPID		(16*32+22) /* RDPID instruction */

#define X86_FEATURE_BUS_LOCK_DETECT	(16*32+24) /* Bus Lock detect */

#define X86_FEATURE_CLDEMOTE		(16*32+25) /* CLDEMOTE instruction */

#define X86_FEATURE_MOVDIRI		(16*32+27) /* MOVDIRI instruction */

#define X86_FEATURE_MOVDIR64B		(16*32+28) /* MOVDIR64B instruction */

arch/x86/include/asm/msr-index.h

+1 −0
Original line number Diff line number Diff line
@@ -265,6 +265,7 @@ 
#define DEBUGCTLMSR_LBR			(1UL <<  0) /* last branch recording */

#define DEBUGCTLMSR_BTF_SHIFT		1

#define DEBUGCTLMSR_BTF			(1UL <<  1) /* single-step on branches */

#define DEBUGCTLMSR_BUS_LOCK_DETECT	(1UL <<  2)

#define DEBUGCTLMSR_TR			(1UL <<  6)

#define DEBUGCTLMSR_BTS			(1UL <<  7)

#define DEBUGCTLMSR_BTINT		(1UL <<  8)

arch/x86/include/uapi/asm/debugreg.h

+1 −0
Original line number Diff line number Diff line
@@ -24,6 +24,7 @@ 
#define DR_TRAP3	(0x8)		/* db3 */

#define DR_TRAP_BITS	(DR_TRAP0|DR_TRAP1|DR_TRAP2|DR_TRAP3)



#define DR_BUS_LOCK	(0x800)		/* bus_lock */

#define DR_STEP		(0x4000)	/* single-step */

#define DR_SWITCH	(0x8000)	/* task switch */