Commit 64fa6b93 authored by Catalin Marinas's avatar Catalin Marinas
Browse files

Merge branch 'for-next/el2-enable-feat-pmuv3p9' into for-next/core 

* for-next/el2-enable-feat-pmuv3p9:
  : Enable EL2 requirements for FEAT_PMUv3p9
  arm64/boot: Enable EL2 requirements for FEAT_PMUv3p9
parents 8ae9e2d8 858c7bfc

Documentation/arch/arm64/booting.rst

+22 −0
Original line number Diff line number Diff line
@@ -288,6 +288,12 @@ Before jumping into the kernel, the following conditions must be met: 


    - SCR_EL3.FGTEn (bit 27) must be initialised to 0b1.



  For CPUs with the Fine Grained Traps 2 (FEAT_FGT2) extension present:



  - If EL3 is present and the kernel is entered at EL2:



    - SCR_EL3.FGTEn2 (bit 59) must be initialised to 0b1.



  For CPUs with support for HCRX_EL2 (FEAT_HCX) present:



  - If EL3 is present and the kernel is entered at EL2:
@@ -382,6 +388,22 @@ Before jumping into the kernel, the following conditions must be met: 


    - SMCR_EL2.EZT0 (bit 30) must be initialised to 0b1.



  For CPUs with the Performance Monitors Extension (FEAT_PMUv3p9):



 - If EL3 is present:



    - MDCR_EL3.EnPM2 (bit 7) must be initialised to 0b1.



 - If the kernel is entered at EL1 and EL2 is present:



    - HDFGRTR2_EL2.nPMICNTR_EL0 (bit 2) must be initialised to 0b1.

    - HDFGRTR2_EL2.nPMICFILTR_EL0 (bit 3) must be initialised to 0b1.

    - HDFGRTR2_EL2.nPMUACR_EL1 (bit 4) must be initialised to 0b1.



    - HDFGWTR2_EL2.nPMICNTR_EL0 (bit 2) must be initialised to 0b1.

    - HDFGWTR2_EL2.nPMICFILTR_EL0 (bit 3) must be initialised to 0b1.

    - HDFGWTR2_EL2.nPMUACR_EL1 (bit 4) must be initialised to 0b1.



  For CPUs with Memory Copy and Memory Set instructions (FEAT_MOPS):



  - If the kernel is entered at EL1 and EL2 is present:

arch/arm64/include/asm/el2_setup.h

+25 −0
Original line number Diff line number Diff line
@@ -233,6 +233,30 @@ 
.Lskip_fgt_\@:

.endm



.macro __init_el2_fgt2

	mrs	x1, id_aa64mmfr0_el1

	ubfx	x1, x1, #ID_AA64MMFR0_EL1_FGT_SHIFT, #4

	cmp	x1, #ID_AA64MMFR0_EL1_FGT_FGT2

	b.lt	.Lskip_fgt2_\@



	mov	x0, xzr

	mrs	x1, id_aa64dfr0_el1

	ubfx	x1, x1, #ID_AA64DFR0_EL1_PMUVer_SHIFT, #4

	cmp	x1, #ID_AA64DFR0_EL1_PMUVer_V3P9

	b.lt	.Lskip_pmuv3p9_\@



	orr	x0, x0, #HDFGRTR2_EL2_nPMICNTR_EL0

	orr	x0, x0, #HDFGRTR2_EL2_nPMICFILTR_EL0

	orr	x0, x0, #HDFGRTR2_EL2_nPMUACR_EL1

.Lskip_pmuv3p9_\@:

	msr_s   SYS_HDFGRTR2_EL2, x0

	msr_s   SYS_HDFGWTR2_EL2, x0

	msr_s   SYS_HFGRTR2_EL2, xzr

	msr_s   SYS_HFGWTR2_EL2, xzr

	msr_s   SYS_HFGITR2_EL2, xzr

.Lskip_fgt2_\@:

.endm



.macro __init_el2_gcs

	mrs_s	x1, SYS_ID_AA64PFR1_EL1

	ubfx	x1, x1, #ID_AA64PFR1_EL1_GCS_SHIFT, #4
@@ -283,6 +307,7 @@ 
	__init_el2_nvhe_idregs

	__init_el2_cptr

	__init_el2_fgt

	__init_el2_fgt2

        __init_el2_gcs

.endm