Merge tag 'mediatek-drm-next-6.15-v2' of... (64fc5dc8) · Commits · git / linux-net

Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml

+7 −0

Original line number	Diff line number	Diff line
		@@ -27,6 +27,7 @@ properties:
		- mediatek,mt8188-dp-intf
		- mediatek,mt8192-dpi
		- mediatek,mt8195-dp-intf
		- mediatek,mt8195-dpi
		- items:
		- enum:
		- mediatek,mt6795-dpi
		@@ -35,6 +36,10 @@ properties:
		- enum:
		- mediatek,mt8365-dpi
		- const: mediatek,mt8192-dpi
		- items:
		- enum:
		- mediatek,mt8188-dpi
		- const: mediatek,mt8195-dpi

		reg:
		maxItems: 1
		@@ -116,11 +121,13 @@ examples:
		- \|
		#include <dt-bindings/interrupt-controller/arm-gic.h>
		#include <dt-bindings/clock/mt8173-clk.h>
		#include <dt-bindings/power/mt8173-power.h>

		dpi: dpi@1401d000 {
		compatible = "mediatek,mt8173-dpi";
		reg = <0x1401d000 0x1000>;
		interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
		power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
		clocks = <&mmsys CLK_MM_DPI_PIXEL>,
		<&mmsys CLK_MM_DPI_ENGINE>,
		<&apmixedsys CLK_APMIXED_TVDPLL>;

Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml

+3 −0

Original line number	Diff line number	Diff line
		@@ -22,6 +22,9 @@ properties:
		oneOf:
		- enum:
		- mediatek,mt8195-disp-dsc
		- items:
		- const: mediatek,mt8188-disp-dsc
		- const: mediatek,mt8195-disp-dsc

		reg:
		maxItems: 1

drivers/gpu/drm/mediatek/mtk_crtc.c

+5 −2

Original line number	Diff line number	Diff line
		@@ -620,13 +620,16 @@ static void mtk_crtc_update_config(struct mtk_crtc *mtk_crtc, bool needs_vblank)

		mbox_send_message(mtk_crtc->cmdq_client.chan, cmdq_handle);
		mbox_client_txdone(mtk_crtc->cmdq_client.chan, 0);
		goto update_config_out;
		}
		#else
		#endif
		spin_lock_irqsave(&mtk_crtc->config_lock, flags);
		mtk_crtc->config_updating = false;
		spin_unlock_irqrestore(&mtk_crtc->config_lock, flags);
		#endif

		#if IS_REACHABLE(CONFIG_MTK_CMDQ)
		update_config_out:
		#endif
		mutex_unlock(&mtk_crtc->hw_lock);
		}

drivers/gpu/drm/mediatek/mtk_dp.c

+3 −3

Original line number	Diff line number	Diff line
		@@ -1766,7 +1766,7 @@ static int mtk_dp_parse_capabilities(struct mtk_dp *mtk_dp)

		ret = drm_dp_dpcd_readb(&mtk_dp->aux, DP_MSTM_CAP, &val);
		if (ret < 1) {
		drm_err(mtk_dp->drm_dev, "Read mstm cap failed\n");
		dev_err(mtk_dp->dev, "Read mstm cap failed: %zd\n", ret);
		return ret == 0 ? -EIO : ret;
		}

		@@ -1776,7 +1776,7 @@ static int mtk_dp_parse_capabilities(struct mtk_dp *mtk_dp)
		DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0,
		&val);
		if (ret < 1) {
		drm_err(mtk_dp->drm_dev, "Read irq vector failed\n");
		dev_err(mtk_dp->dev, "Read irq vector failed: %zd\n", ret);
		return ret == 0 ? -EIO : ret;
		}

		@@ -2059,7 +2059,7 @@ static int mtk_dp_wait_hpd_asserted(struct drm_dp_aux *mtk_aux, unsigned long wa

		ret = mtk_dp_parse_capabilities(mtk_dp);
		if (ret) {
		drm_err(mtk_dp->drm_dev, "Can't parse capabilities\n");
		dev_err(mtk_dp->dev, "Can't parse capabilities: %d\n", ret);
		return ret;
		}

drivers/gpu/drm/mediatek/mtk_dpi.c

+241 −82

Original line number	Diff line number	Diff line
		@@ -4,8 +4,10 @@
		* Author: Jie Qiu <jie.qiu@mediatek.com>
		*/

		#include <linux/bitfield.h>
		#include <linux/clk.h>
		#include <linux/component.h>
		#include <linux/debugfs.h>
		#include <linux/interrupt.h>
		#include <linux/kernel.h>
		#include <linux/media-bus-format.h>
		@@ -116,9 +118,15 @@ struct mtk_dpi_yc_limit {
		u16 c_bottom;
		};

		struct mtk_dpi_factor {
		u32 clock;
		u8 factor;
		};

		/**
		* struct mtk_dpi_conf - Configuration of mediatek dpi.
		* @cal_factor: Callback function to calculate factor value.
		* @dpi_factor: SoC-specific pixel clock PLL factor values.
		* @num_dpi_factor: Number of pixel clock PLL factor values.
		* @reg_h_fre_con: Register address of frequency control.
		* @max_clock_khz: Max clock frequency supported for this SoCs in khz units.
		* @edge_sel_en: Enable of edge selection.
		@@ -127,19 +135,24 @@ struct mtk_dpi_yc_limit {
		* @is_ck_de_pol: Support CK/DE polarity.
		* @swap_input_support: Support input swap function.
		* @support_direct_pin: IP supports direct connection to dpi panels.
		* @input_2pixel: Input pixel of dp_intf is 2 pixel per round, so enable this
		* config to enable this feature.
		* @dimension_mask: Mask used for HWIDTH, HPORCH, VSYNC_WIDTH and VSYNC_PORCH
		* (no shift).
		* @hvsize_mask: Mask of HSIZE and VSIZE mask (no shift).
		* @channel_swap_shift: Shift value of channel swap.
		* @yuv422_en_bit: Enable bit of yuv422.
		* @csc_enable_bit: Enable bit of CSC.
		* @input_2p_en_bit: Enable bit for input two pixel per round feature.
		* If present, implies that the feature must be enabled.
		* @pixels_per_iter: Quantity of transferred pixels per iteration.
		* @edge_cfg_in_mmsys: If the edge configuration for DPI's output needs to be set in MMSYS.
		* @clocked_by_hdmi: HDMI IP outputs clock to dpi_pixel_clk input clock, needed
		* for DPI registers access.
		* @output_1pixel: Enable outputting one pixel per round; if the input is two pixel per
		* round, the DPI hardware will internally transform it to 1T1P.
		*/
		struct mtk_dpi_conf {
		unsigned int (*cal_factor)(int clock);
		const struct mtk_dpi_factor *dpi_factor;
		const u8 num_dpi_factor;
		u32 reg_h_fre_con;
		u32 max_clock_khz;
		bool edge_sel_en;
		@@ -148,14 +161,16 @@ struct mtk_dpi_conf {
		bool is_ck_de_pol;
		bool swap_input_support;
		bool support_direct_pin;
		bool input_2pixel;
		u32 dimension_mask;
		u32 hvsize_mask;
		u32 channel_swap_shift;
		u32 yuv422_en_bit;
		u32 csc_enable_bit;
		u32 input_2p_en_bit;
		u32 pixels_per_iter;
		bool edge_cfg_in_mmsys;
		bool clocked_by_hdmi;
		bool output_1pixel;
		};

		static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask)
		@@ -166,6 +181,18 @@ static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask)
		writel(tmp, dpi->regs + offset);
		}

		static void mtk_dpi_test_pattern_en(struct mtk_dpi *dpi, u8 type, bool enable)
		{
		u32 val;

		if (enable)
		val = FIELD_PREP(DPI_PAT_SEL, type) \| DPI_PAT_EN;
		else
		val = 0;

		mtk_dpi_mask(dpi, DPI_PATTERN0, val, DPI_PAT_SEL \| DPI_PAT_EN);
		}

		static void mtk_dpi_sw_reset(struct mtk_dpi *dpi, bool reset)
		{
		mtk_dpi_mask(dpi, DPI_RET, reset ? RST : 0, RST);
		@@ -410,12 +437,13 @@ static void mtk_dpi_config_swap_input(struct mtk_dpi *dpi, bool enable)

		static void mtk_dpi_config_2n_h_fre(struct mtk_dpi *dpi)
		{
		if (dpi->conf->reg_h_fre_con)
		mtk_dpi_mask(dpi, dpi->conf->reg_h_fre_con, H_FRE_2N, H_FRE_2N);
		}

		static void mtk_dpi_config_disable_edge(struct mtk_dpi *dpi)
		{
		if (dpi->conf->edge_sel_en)
		if (dpi->conf->edge_sel_en && dpi->conf->reg_h_fre_con)
		mtk_dpi_mask(dpi, dpi->conf->reg_h_fre_con, 0, EDGE_SEL_EN);
		}

		@@ -471,6 +499,7 @@ static void mtk_dpi_power_off(struct mtk_dpi *dpi)

		mtk_dpi_disable(dpi);
		clk_disable_unprepare(dpi->pixel_clk);
		clk_disable_unprepare(dpi->tvd_clk);
		clk_disable_unprepare(dpi->engine_clk);
		}

		@@ -487,6 +516,12 @@ static int mtk_dpi_power_on(struct mtk_dpi *dpi)
		goto err_refcount;
		}

		ret = clk_prepare_enable(dpi->tvd_clk);
		if (ret) {
		dev_err(dpi->dev, "Failed to enable tvd pll: %d\n", ret);
		goto err_engine;
		}

		ret = clk_prepare_enable(dpi->pixel_clk);
		if (ret) {
		dev_err(dpi->dev, "Failed to enable pixel clock: %d\n", ret);
		@@ -496,32 +531,39 @@ static int mtk_dpi_power_on(struct mtk_dpi *dpi)
		return 0;

		err_pixel:
		clk_disable_unprepare(dpi->tvd_clk);
		err_engine:
		clk_disable_unprepare(dpi->engine_clk);
		err_refcount:
		dpi->refcount--;
		return ret;
		}

		static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
		struct drm_display_mode *mode)
		static unsigned int mtk_dpi_calculate_factor(struct mtk_dpi *dpi, int mode_clk)
		{
		const struct mtk_dpi_factor *dpi_factor = dpi->conf->dpi_factor;
		int i;

		for (i = 0; i < dpi->conf->num_dpi_factor; i++) {
		if (mode_clk <= dpi_factor[i].clock)
		return dpi_factor[i].factor;
		}

		/* If no match try the lowest possible factor */
		return dpi_factor[dpi->conf->num_dpi_factor - 1].factor;
		}

		static void mtk_dpi_set_pixel_clk(struct mtk_dpi dpi, struct videomode vm, int mode_clk)
		{
		struct mtk_dpi_polarities dpi_pol;
		struct mtk_dpi_sync_param hsync;
		struct mtk_dpi_sync_param vsync_lodd = { 0 };
		struct mtk_dpi_sync_param vsync_leven = { 0 };
		struct mtk_dpi_sync_param vsync_rodd = { 0 };
		struct mtk_dpi_sync_param vsync_reven = { 0 };
		struct videomode vm = { 0 };
		unsigned long pll_rate;
		unsigned int factor;

		/* let pll_rate can fix the valid range of tvdpll (1G~2GHz) */
		factor = dpi->conf->cal_factor(mode->clock);
		drm_display_mode_to_videomode(mode, &vm);
		pll_rate = vm.pixelclock * factor;
		factor = mtk_dpi_calculate_factor(dpi, mode_clk);
		pll_rate = vm->pixelclock * factor;

		dev_dbg(dpi->dev, "Want PLL %lu Hz, pixel clock %lu Hz\n",
		pll_rate, vm.pixelclock);
		pll_rate, vm->pixelclock);

		clk_set_rate(dpi->tvd_clk, pll_rate);
		pll_rate = clk_get_rate(dpi->tvd_clk);
		@@ -531,20 +573,36 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
		* pixels for each iteration: divide the clock by this number and
		* adjust the display porches accordingly.
		*/
		vm.pixelclock = pll_rate / factor;
		vm.pixelclock /= dpi->conf->pixels_per_iter;
		vm->pixelclock = pll_rate / factor;
		vm->pixelclock /= dpi->conf->pixels_per_iter;

		if ((dpi->output_fmt == MEDIA_BUS_FMT_RGB888_2X12_LE) \|\|
		(dpi->output_fmt == MEDIA_BUS_FMT_RGB888_2X12_BE))
		clk_set_rate(dpi->pixel_clk, vm.pixelclock * 2);
		clk_set_rate(dpi->pixel_clk, vm->pixelclock * 2);
		else
		clk_set_rate(dpi->pixel_clk, vm.pixelclock);
		clk_set_rate(dpi->pixel_clk, vm->pixelclock);


		vm.pixelclock = clk_get_rate(dpi->pixel_clk);
		vm->pixelclock = clk_get_rate(dpi->pixel_clk);

		dev_dbg(dpi->dev, "Got PLL %lu Hz, pixel clock %lu Hz\n",
		pll_rate, vm.pixelclock);
		pll_rate, vm->pixelclock);
		}

		static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
		struct drm_display_mode *mode)
		{
		struct mtk_dpi_polarities dpi_pol;
		struct mtk_dpi_sync_param hsync;
		struct mtk_dpi_sync_param vsync_lodd = { 0 };
		struct mtk_dpi_sync_param vsync_leven = { 0 };
		struct mtk_dpi_sync_param vsync_rodd = { 0 };
		struct mtk_dpi_sync_param vsync_reven = { 0 };
		struct videomode vm = { 0 };

		drm_display_mode_to_videomode(mode, &vm);

		if (!dpi->conf->clocked_by_hdmi)
		mtk_dpi_set_pixel_clk(dpi, &vm, mode->clock);

		dpi_pol.ck_pol = MTK_DPI_POLARITY_FALLING;
		dpi_pol.de_pol = MTK_DPI_POLARITY_RISING;
		@@ -607,12 +665,18 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
		if (dpi->conf->support_direct_pin) {
		mtk_dpi_config_yc_map(dpi, dpi->yc_map);
		mtk_dpi_config_2n_h_fre(dpi);

		/* DPI can connect to either an external bridge or the internal HDMI encoder */
		if (dpi->conf->output_1pixel)
		mtk_dpi_mask(dpi, DPI_CON, DPI_OUTPUT_1T1P_EN, DPI_OUTPUT_1T1P_EN);
		else
		mtk_dpi_dual_edge(dpi);

		mtk_dpi_config_disable_edge(dpi);
		}
		if (dpi->conf->input_2pixel) {
		mtk_dpi_mask(dpi, DPI_CON, DPINTF_INPUT_2P_EN,
		DPINTF_INPUT_2P_EN);
		if (dpi->conf->input_2p_en_bit) {
		mtk_dpi_mask(dpi, DPI_CON, dpi->conf->input_2p_en_bit,
		dpi->conf->input_2p_en_bit);
		}
		mtk_dpi_sw_reset(dpi, false);

		@@ -767,6 +831,99 @@ mtk_dpi_bridge_mode_valid(struct drm_bridge *bridge,
		return MODE_OK;
		}

		static int mtk_dpi_debug_tp_show(struct seq_file m, void arg)
		{
		struct mtk_dpi *dpi = m->private;
		bool en;
		u32 val;

		if (!dpi)
		return -EINVAL;

		val = readl(dpi->regs + DPI_PATTERN0);
		en = val & DPI_PAT_EN;
		val = FIELD_GET(DPI_PAT_SEL, val);

		seq_printf(m, "DPI Test Pattern: %s\n", en ? "Enabled" : "Disabled");

		if (en) {
		seq_printf(m, "Internal pattern %d: ", val);
		switch (val) {
		case 0:
		seq_puts(m, "256 Vertical Gray\n");
		break;
		case 1:
		seq_puts(m, "1024 Vertical Gray\n");
		break;
		case 2:
		seq_puts(m, "256 Horizontal Gray\n");
		break;
		case 3:
		seq_puts(m, "1024 Horizontal Gray\n");
		break;
		case 4:
		seq_puts(m, "Vertical Color bars\n");
		break;
		case 6:
		seq_puts(m, "Frame border\n");
		break;
		case 7:
		seq_puts(m, "Dot moire\n");
		break;
		default:
		seq_puts(m, "Invalid selection\n");
		break;
		}
		}

		return 0;
		}

		static ssize_t mtk_dpi_debug_tp_write(struct file file, const char __user ubuf,
		size_t len, loff_t *offp)
		{
		struct seq_file *m = file->private_data;
		u32 en, type;
		char buf[6];

		if (!m \|\| !m->private \|\| *offp \|\| len > sizeof(buf) - 1)
		return -EINVAL;

		memset(buf, 0, sizeof(buf));
		if (copy_from_user(buf, ubuf, len))
		return -EFAULT;

		if (sscanf(buf, "%u %u", &en, &type) != 2)
		return -EINVAL;

		if (en < 0 \|\| en > 1 \|\| type < 0 \|\| type > 7)
		return -EINVAL;

		mtk_dpi_test_pattern_en((struct mtk_dpi *)m->private, type, en);
		return len;
		}

		static int mtk_dpi_debug_tp_open(struct inode inode, struct file file)
		{
		return single_open(file, mtk_dpi_debug_tp_show, inode->i_private);
		}

		static const struct file_operations mtk_dpi_debug_tp_fops = {
		.owner = THIS_MODULE,
		.open = mtk_dpi_debug_tp_open,
		.read = seq_read,
		.write = mtk_dpi_debug_tp_write,
		.llseek = seq_lseek,
		.release = single_release,
		};

		static void mtk_dpi_debugfs_init(struct drm_bridge bridge, struct dentry root)
		{
		struct mtk_dpi *dpi = bridge_to_dpi(bridge);

		debugfs_create_file("dpi_test_pattern", 0640, root, dpi, &mtk_dpi_debug_tp_fops);
		}

		static const struct drm_bridge_funcs mtk_dpi_bridge_funcs = {
		.attach = mtk_dpi_bridge_attach,
		.mode_set = mtk_dpi_bridge_mode_set,
		@@ -779,12 +936,14 @@ static const struct drm_bridge_funcs mtk_dpi_bridge_funcs = {
		.atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
		.atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
		.atomic_reset = drm_atomic_helper_bridge_reset,
		.debugfs_init = mtk_dpi_debugfs_init,
		};

		void mtk_dpi_start(struct device *dev)
		{
		struct mtk_dpi *dpi = dev_get_drvdata(dev);

		if (!dpi->conf->clocked_by_hdmi)
		mtk_dpi_power_on(dpi);
		}

		@@ -792,6 +951,7 @@ void mtk_dpi_stop(struct device *dev)
		{
		struct mtk_dpi *dpi = dev_get_drvdata(dev);

		if (!dpi->conf->clocked_by_hdmi)
		mtk_dpi_power_off(dpi);
		}

		@@ -857,48 +1017,6 @@ static const struct component_ops mtk_dpi_component_ops = {
		.unbind = mtk_dpi_unbind,
		};

		static unsigned int mt8173_calculate_factor(int clock)
		{
		if (clock <= 27000)
		return 3 << 4;
		else if (clock <= 84000)
		return 3 << 3;
		else if (clock <= 167000)
		return 3 << 2;
		else
		return 3 << 1;
		}

		static unsigned int mt2701_calculate_factor(int clock)
		{
		if (clock <= 64000)
		return 4;
		else if (clock <= 128000)
		return 2;
		else
		return 1;
		}

		static unsigned int mt8183_calculate_factor(int clock)
		{
		if (clock <= 27000)
		return 8;
		else if (clock <= 167000)
		return 4;
		else
		return 2;
		}

		static unsigned int mt8195_dpintf_calculate_factor(int clock)
		{
		if (clock < 70000)
		return 4;
		else if (clock < 200000)
		return 2;
		else
		return 1;
		}

		static const u32 mt8173_output_fmts[] = {
		MEDIA_BUS_FMT_RGB888_1X24,
		};
		@@ -913,8 +1031,25 @@ static const u32 mt8195_output_fmts[] = {
		MEDIA_BUS_FMT_YUYV8_1X16,
		};

		static const struct mtk_dpi_factor dpi_factor_mt2701[] = {
		{ 64000, 4 }, { 128000, 2 }, { U32_MAX, 1 }
		};

		static const struct mtk_dpi_factor dpi_factor_mt8173[] = {
		{ 27000, 48 }, { 84000, 24 }, { 167000, 12 }, { U32_MAX, 6 }
		};

		static const struct mtk_dpi_factor dpi_factor_mt8183[] = {
		{ 27000, 8 }, { 167000, 4 }, { U32_MAX, 2 }
		};

		static const struct mtk_dpi_factor dpi_factor_mt8195_dp_intf[] = {
		{ 70000 - 1, 4 }, { 200000 - 1, 2 }, { U32_MAX, 1 }
		};

		static const struct mtk_dpi_conf mt8173_conf = {
		.cal_factor = mt8173_calculate_factor,
		.dpi_factor = dpi_factor_mt8173,
		.num_dpi_factor = ARRAY_SIZE(dpi_factor_mt8173),
		.reg_h_fre_con = 0xe0,
		.max_clock_khz = 300000,
		.output_fmts = mt8173_output_fmts,
		@@ -931,7 +1066,8 @@ static const struct mtk_dpi_conf mt8173_conf = {
		};

		static const struct mtk_dpi_conf mt2701_conf = {
		.cal_factor = mt2701_calculate_factor,
		.dpi_factor = dpi_factor_mt2701,
		.num_dpi_factor = ARRAY_SIZE(dpi_factor_mt2701),
		.reg_h_fre_con = 0xb0,
		.edge_sel_en = true,
		.max_clock_khz = 150000,
		@@ -949,7 +1085,8 @@ static const struct mtk_dpi_conf mt2701_conf = {
		};

		static const struct mtk_dpi_conf mt8183_conf = {
		.cal_factor = mt8183_calculate_factor,
		.dpi_factor = dpi_factor_mt8183,
		.num_dpi_factor = ARRAY_SIZE(dpi_factor_mt8183),
		.reg_h_fre_con = 0xe0,
		.max_clock_khz = 100000,
		.output_fmts = mt8183_output_fmts,
		@@ -966,7 +1103,8 @@ static const struct mtk_dpi_conf mt8183_conf = {
		};

		static const struct mtk_dpi_conf mt8186_conf = {
		.cal_factor = mt8183_calculate_factor,
		.dpi_factor = dpi_factor_mt8183,
		.num_dpi_factor = ARRAY_SIZE(dpi_factor_mt8183),
		.reg_h_fre_con = 0xe0,
		.max_clock_khz = 150000,
		.output_fmts = mt8183_output_fmts,
		@@ -984,7 +1122,8 @@ static const struct mtk_dpi_conf mt8186_conf = {
		};

		static const struct mtk_dpi_conf mt8192_conf = {
		.cal_factor = mt8183_calculate_factor,
		.dpi_factor = dpi_factor_mt8183,
		.num_dpi_factor = ARRAY_SIZE(dpi_factor_mt8183),
		.reg_h_fre_con = 0xe0,
		.max_clock_khz = 150000,
		.output_fmts = mt8183_output_fmts,
		@@ -1000,18 +1139,37 @@ static const struct mtk_dpi_conf mt8192_conf = {
		.csc_enable_bit = CSC_ENABLE,
		};

		static const struct mtk_dpi_conf mt8195_conf = {
		.max_clock_khz = 594000,
		.output_fmts = mt8183_output_fmts,
		.num_output_fmts = ARRAY_SIZE(mt8183_output_fmts),
		.pixels_per_iter = 1,
		.is_ck_de_pol = true,
		.swap_input_support = true,
		.support_direct_pin = true,
		.dimension_mask = HPW_MASK,
		.hvsize_mask = HSIZE_MASK,
		.channel_swap_shift = CH_SWAP,
		.yuv422_en_bit = YUV422_EN,
		.csc_enable_bit = CSC_ENABLE,
		.input_2p_en_bit = DPI_INPUT_2P_EN,
		.clocked_by_hdmi = true,
		.output_1pixel = true,
		};

		static const struct mtk_dpi_conf mt8195_dpintf_conf = {
		.cal_factor = mt8195_dpintf_calculate_factor,
		.dpi_factor = dpi_factor_mt8195_dp_intf,
		.num_dpi_factor = ARRAY_SIZE(dpi_factor_mt8195_dp_intf),
		.max_clock_khz = 600000,
		.output_fmts = mt8195_output_fmts,
		.num_output_fmts = ARRAY_SIZE(mt8195_output_fmts),
		.pixels_per_iter = 4,
		.input_2pixel = true,
		.dimension_mask = DPINTF_HPW_MASK,
		.hvsize_mask = DPINTF_HSIZE_MASK,
		.channel_swap_shift = DPINTF_CH_SWAP,
		.yuv422_en_bit = DPINTF_YUV422_EN,
		.csc_enable_bit = DPINTF_CSC_ENABLE,
		.input_2p_en_bit = DPINTF_INPUT_2P_EN,
		};

		static int mtk_dpi_probe(struct platform_device *pdev)
		@@ -1102,6 +1260,7 @@ static const struct of_device_id mtk_dpi_of_ids[] = {
		{ .compatible = "mediatek,mt8188-dp-intf", .data = &mt8195_dpintf_conf },
		{ .compatible = "mediatek,mt8192-dpi", .data = &mt8192_conf },
		{ .compatible = "mediatek,mt8195-dp-intf", .data = &mt8195_dpintf_conf },
		{ .compatible = "mediatek,mt8195-dpi", .data = &mt8195_conf },
		{ /* sentinel */ },
		};
		MODULE_DEVICE_TABLE(of, mtk_dpi_of_ids);