Commit 65164fd0 authored by Paolo Bonzini's avatar Paolo Bonzini
Browse files

Merge tag 'kvm-riscv-6.17-2' of https://github.com/kvm-riscv/linux into HEAD 

KVM/riscv changes for 6.17

- Enabled ring-based dirty memory tracking
- Improved perf kvm stat to report interrupt events
- Delegate illegal instruction trap to VS-mode
- MMU related improvements for KVM RISC-V for upcoming
  nested virtualization
parents 038d61fd 07a289a0

Documentation/virt/kvm/api.rst

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@@ -8387,7 +8387,7 @@ core crystal clock frequency, if a non-zero CPUID 0x15 is exposed to the guest. 
7.36 KVM_CAP_DIRTY_LOG_RING/KVM_CAP_DIRTY_LOG_RING_ACQ_REL

----------------------------------------------------------



:Architectures: x86, arm64

:Architectures: x86, arm64, riscv

:Type: vm

:Parameters: args[0] - size of the dirty log ring

arch/riscv/include/asm/kvm_aia.h

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@@ -150,7 +150,7 @@ int kvm_riscv_vcpu_aia_rmw_ireg(struct kvm_vcpu *vcpu, unsigned int csr_num, 


int kvm_riscv_vcpu_aia_update(struct kvm_vcpu *vcpu);

void kvm_riscv_vcpu_aia_reset(struct kvm_vcpu *vcpu);

int kvm_riscv_vcpu_aia_init(struct kvm_vcpu *vcpu);

void kvm_riscv_vcpu_aia_init(struct kvm_vcpu *vcpu);

void kvm_riscv_vcpu_aia_deinit(struct kvm_vcpu *vcpu);



int kvm_riscv_aia_inject_msi_by_id(struct kvm *kvm, u32 hart_index,

arch/riscv/include/asm/kvm_gstage.h

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/* SPDX-License-Identifier: GPL-2.0-only */

/*

 * Copyright (C) 2019 Western Digital Corporation or its affiliates.

 * Copyright (c) 2025 Ventana Micro Systems Inc.

 */



#ifndef __RISCV_KVM_GSTAGE_H_

#define __RISCV_KVM_GSTAGE_H_



#include <linux/kvm_types.h>



struct kvm_gstage {

	struct kvm *kvm;

	unsigned long flags;

#define KVM_GSTAGE_FLAGS_LOCAL		BIT(0)

	unsigned long vmid;

	pgd_t *pgd;

};



struct kvm_gstage_mapping {

	gpa_t addr;

	pte_t pte;

	u32 level;

};



#ifdef CONFIG_64BIT

#define kvm_riscv_gstage_index_bits	9

#else

#define kvm_riscv_gstage_index_bits	10

#endif



extern unsigned long kvm_riscv_gstage_mode;

extern unsigned long kvm_riscv_gstage_pgd_levels;



#define kvm_riscv_gstage_pgd_xbits	2

#define kvm_riscv_gstage_pgd_size	(1UL << (HGATP_PAGE_SHIFT + kvm_riscv_gstage_pgd_xbits))

#define kvm_riscv_gstage_gpa_bits	(HGATP_PAGE_SHIFT + \

					 (kvm_riscv_gstage_pgd_levels * \

					  kvm_riscv_gstage_index_bits) + \

					 kvm_riscv_gstage_pgd_xbits)

#define kvm_riscv_gstage_gpa_size	((gpa_t)(1ULL << kvm_riscv_gstage_gpa_bits))



bool kvm_riscv_gstage_get_leaf(struct kvm_gstage *gstage, gpa_t addr,

			       pte_t **ptepp, u32 *ptep_level);



int kvm_riscv_gstage_set_pte(struct kvm_gstage *gstage,

			     struct kvm_mmu_memory_cache *pcache,

			     const struct kvm_gstage_mapping *map);



int kvm_riscv_gstage_map_page(struct kvm_gstage *gstage,

			      struct kvm_mmu_memory_cache *pcache,

			      gpa_t gpa, phys_addr_t hpa, unsigned long page_size,

			      bool page_rdonly, bool page_exec,

			      struct kvm_gstage_mapping *out_map);



enum kvm_riscv_gstage_op {

	GSTAGE_OP_NOP = 0,	/* Nothing */

	GSTAGE_OP_CLEAR,	/* Clear/Unmap */

	GSTAGE_OP_WP,		/* Write-protect */

};



void kvm_riscv_gstage_op_pte(struct kvm_gstage *gstage, gpa_t addr,

			     pte_t *ptep, u32 ptep_level, enum kvm_riscv_gstage_op op);



void kvm_riscv_gstage_unmap_range(struct kvm_gstage *gstage,

				  gpa_t start, gpa_t size, bool may_block);



void kvm_riscv_gstage_wp_range(struct kvm_gstage *gstage, gpa_t start, gpa_t end);



void kvm_riscv_gstage_mode_detect(void);



#endif

arch/riscv/include/asm/kvm_host.h

+5 −100
Original line number Diff line number Diff line
@@ -16,6 +16,8 @@ 
#include <asm/hwcap.h>

#include <asm/kvm_aia.h>

#include <asm/ptrace.h>

#include <asm/kvm_tlb.h>

#include <asm/kvm_vmid.h>

#include <asm/kvm_vcpu_fp.h>

#include <asm/kvm_vcpu_insn.h>

#include <asm/kvm_vcpu_sbi.h>
@@ -36,14 +38,16 @@ 
#define KVM_REQ_UPDATE_HGATP		KVM_ARCH_REQ(2)

#define KVM_REQ_FENCE_I			\

	KVM_ARCH_REQ_FLAGS(3, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP)

#define KVM_REQ_HFENCE_GVMA_VMID_ALL	KVM_REQ_TLB_FLUSH

#define KVM_REQ_HFENCE_VVMA_ALL		\

	KVM_ARCH_REQ_FLAGS(4, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP)

#define KVM_REQ_HFENCE			\

	KVM_ARCH_REQ_FLAGS(5, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP)

#define KVM_REQ_STEAL_UPDATE		KVM_ARCH_REQ(6)



#define __KVM_HAVE_ARCH_FLUSH_REMOTE_TLBS_RANGE



#define KVM_HEDELEG_DEFAULT		(BIT(EXC_INST_MISALIGNED) | \

					 BIT(EXC_INST_ILLEGAL)     | \

					 BIT(EXC_BREAKPOINT)      | \

					 BIT(EXC_SYSCALL)         | \

					 BIT(EXC_INST_PAGE_FAULT) | \
@@ -54,24 +58,6 @@ 
					 BIT(IRQ_VS_TIMER) | \

					 BIT(IRQ_VS_EXT))



enum kvm_riscv_hfence_type {

	KVM_RISCV_HFENCE_UNKNOWN = 0,

	KVM_RISCV_HFENCE_GVMA_VMID_GPA,

	KVM_RISCV_HFENCE_VVMA_ASID_GVA,

	KVM_RISCV_HFENCE_VVMA_ASID_ALL,

	KVM_RISCV_HFENCE_VVMA_GVA,

};



struct kvm_riscv_hfence {

	enum kvm_riscv_hfence_type type;

	unsigned long asid;

	unsigned long order;

	gpa_t addr;

	gpa_t size;

};



#define KVM_RISCV_VCPU_MAX_HFENCE	64



struct kvm_vm_stat {

	struct kvm_vm_stat_generic generic;

};
@@ -97,15 +83,6 @@ struct kvm_vcpu_stat { 
struct kvm_arch_memory_slot {

};



struct kvm_vmid {

	/*

	 * Writes to vmid_version and vmid happen with vmid_lock held

	 * whereas reads happen without any lock held.

	 */

	unsigned long vmid_version;

	unsigned long vmid;

};



struct kvm_arch {

	/* G-stage vmid */

	struct kvm_vmid vmid;
@@ -309,77 +286,6 @@ static inline bool kvm_arch_pmi_in_guest(struct kvm_vcpu *vcpu) 
static inline void kvm_arch_vcpu_blocking(struct kvm_vcpu *vcpu) {}

static inline void kvm_arch_vcpu_unblocking(struct kvm_vcpu *vcpu) {}



#define KVM_RISCV_GSTAGE_TLB_MIN_ORDER		12



void kvm_riscv_local_hfence_gvma_vmid_gpa(unsigned long vmid,

					  gpa_t gpa, gpa_t gpsz,

					  unsigned long order);

void kvm_riscv_local_hfence_gvma_vmid_all(unsigned long vmid);

void kvm_riscv_local_hfence_gvma_gpa(gpa_t gpa, gpa_t gpsz,

				     unsigned long order);

void kvm_riscv_local_hfence_gvma_all(void);

void kvm_riscv_local_hfence_vvma_asid_gva(unsigned long vmid,

					  unsigned long asid,

					  unsigned long gva,

					  unsigned long gvsz,

					  unsigned long order);

void kvm_riscv_local_hfence_vvma_asid_all(unsigned long vmid,

					  unsigned long asid);

void kvm_riscv_local_hfence_vvma_gva(unsigned long vmid,

				     unsigned long gva, unsigned long gvsz,

				     unsigned long order);

void kvm_riscv_local_hfence_vvma_all(unsigned long vmid);



void kvm_riscv_local_tlb_sanitize(struct kvm_vcpu *vcpu);



void kvm_riscv_fence_i_process(struct kvm_vcpu *vcpu);

void kvm_riscv_hfence_gvma_vmid_all_process(struct kvm_vcpu *vcpu);

void kvm_riscv_hfence_vvma_all_process(struct kvm_vcpu *vcpu);

void kvm_riscv_hfence_process(struct kvm_vcpu *vcpu);



void kvm_riscv_fence_i(struct kvm *kvm,

		       unsigned long hbase, unsigned long hmask);

void kvm_riscv_hfence_gvma_vmid_gpa(struct kvm *kvm,

				    unsigned long hbase, unsigned long hmask,

				    gpa_t gpa, gpa_t gpsz,

				    unsigned long order);

void kvm_riscv_hfence_gvma_vmid_all(struct kvm *kvm,

				    unsigned long hbase, unsigned long hmask);

void kvm_riscv_hfence_vvma_asid_gva(struct kvm *kvm,

				    unsigned long hbase, unsigned long hmask,

				    unsigned long gva, unsigned long gvsz,

				    unsigned long order, unsigned long asid);

void kvm_riscv_hfence_vvma_asid_all(struct kvm *kvm,

				    unsigned long hbase, unsigned long hmask,

				    unsigned long asid);

void kvm_riscv_hfence_vvma_gva(struct kvm *kvm,

			       unsigned long hbase, unsigned long hmask,

			       unsigned long gva, unsigned long gvsz,

			       unsigned long order);

void kvm_riscv_hfence_vvma_all(struct kvm *kvm,

			       unsigned long hbase, unsigned long hmask);



int kvm_riscv_gstage_ioremap(struct kvm *kvm, gpa_t gpa,

			     phys_addr_t hpa, unsigned long size,

			     bool writable, bool in_atomic);

void kvm_riscv_gstage_iounmap(struct kvm *kvm, gpa_t gpa,

			      unsigned long size);

int kvm_riscv_gstage_map(struct kvm_vcpu *vcpu,

			 struct kvm_memory_slot *memslot,

			 gpa_t gpa, unsigned long hva, bool is_write);

int kvm_riscv_gstage_alloc_pgd(struct kvm *kvm);

void kvm_riscv_gstage_free_pgd(struct kvm *kvm);

void kvm_riscv_gstage_update_hgatp(struct kvm_vcpu *vcpu);

void __init kvm_riscv_gstage_mode_detect(void);

unsigned long __init kvm_riscv_gstage_mode(void);

int kvm_riscv_gstage_gpa_bits(void);



void __init kvm_riscv_gstage_vmid_detect(void);

unsigned long kvm_riscv_gstage_vmid_bits(void);

int kvm_riscv_gstage_vmid_init(struct kvm *kvm);

bool kvm_riscv_gstage_vmid_ver_changed(struct kvm_vmid *vmid);

void kvm_riscv_gstage_vmid_update(struct kvm_vcpu *vcpu);



int kvm_riscv_setup_default_irq_routing(struct kvm *kvm, u32 lines);



void __kvm_riscv_unpriv_trap(void);
@@ -415,7 +321,6 @@ void __kvm_riscv_vcpu_power_on(struct kvm_vcpu *vcpu); 
void kvm_riscv_vcpu_power_on(struct kvm_vcpu *vcpu);

bool kvm_riscv_vcpu_stopped(struct kvm_vcpu *vcpu);



void kvm_riscv_vcpu_sbi_sta_reset(struct kvm_vcpu *vcpu);

void kvm_riscv_vcpu_record_steal_time(struct kvm_vcpu *vcpu);



#endif /* __RISCV_KVM_HOST_H__ */

arch/riscv/include/asm/kvm_mmu.h

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/* SPDX-License-Identifier: GPL-2.0-only */

/*

 * Copyright (c) 2025 Ventana Micro Systems Inc.

 */



#ifndef __RISCV_KVM_MMU_H_

#define __RISCV_KVM_MMU_H_



#include <asm/kvm_gstage.h>



int kvm_riscv_mmu_ioremap(struct kvm *kvm, gpa_t gpa, phys_addr_t hpa,

			  unsigned long size, bool writable, bool in_atomic);

void kvm_riscv_mmu_iounmap(struct kvm *kvm, gpa_t gpa, unsigned long size);

int kvm_riscv_mmu_map(struct kvm_vcpu *vcpu, struct kvm_memory_slot *memslot,

		      gpa_t gpa, unsigned long hva, bool is_write,

		      struct kvm_gstage_mapping *out_map);

int kvm_riscv_mmu_alloc_pgd(struct kvm *kvm);

void kvm_riscv_mmu_free_pgd(struct kvm *kvm);

void kvm_riscv_mmu_update_hgatp(struct kvm_vcpu *vcpu);



#endif