Commit 6535348a authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/amdgpu/mes: remove more unused functions 



These were leftover from mes bring up and are unused.

Reviewed-by: default avatarSunil Khatri <sunil.khatri@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 4e24c6bb

drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c

+0 −62
Original line number Diff line number Diff line
@@ -285,68 +285,6 @@ int amdgpu_mes_resume(struct amdgpu_device *adev) 
	return r;

}



int amdgpu_mes_reset_hw_queue(struct amdgpu_device *adev, int queue_id)

{

	unsigned long flags;

	struct amdgpu_mes_queue *queue;

	struct amdgpu_mes_gang *gang;

	struct mes_reset_queue_input queue_input;

	int r;



	/*

	 * Avoid taking any other locks under MES lock to avoid circular

	 * lock dependencies.

	 */

	amdgpu_mes_lock(&adev->mes);



	/* remove the mes gang from idr list */

	spin_lock_irqsave(&adev->mes.queue_id_lock, flags);



	queue = idr_find(&adev->mes.queue_id_idr, queue_id);

	if (!queue) {

		spin_unlock_irqrestore(&adev->mes.queue_id_lock, flags);

		amdgpu_mes_unlock(&adev->mes);

		DRM_ERROR("queue id %d doesn't exist\n", queue_id);

		return -EINVAL;

	}

	spin_unlock_irqrestore(&adev->mes.queue_id_lock, flags);



	DRM_DEBUG("try to reset queue, doorbell off = 0x%llx\n",

		  queue->doorbell_off);



	gang = queue->gang;

	queue_input.doorbell_offset = queue->doorbell_off;

	queue_input.gang_context_addr = gang->gang_ctx_gpu_addr;



	r = adev->mes.funcs->reset_hw_queue(&adev->mes, &queue_input);

	if (r)

		DRM_ERROR("failed to reset hardware queue, queue id = %d\n",

			  queue_id);



	amdgpu_mes_unlock(&adev->mes);



	return 0;

}



int amdgpu_mes_reset_hw_queue_mmio(struct amdgpu_device *adev, int queue_type,

				   int me_id, int pipe_id, int queue_id, int vmid)

{

	struct mes_reset_queue_input queue_input;

	int r;



	queue_input.queue_type = queue_type;

	queue_input.use_mmio = true;

	queue_input.me_id = me_id;

	queue_input.pipe_id = pipe_id;

	queue_input.queue_id = queue_id;

	queue_input.vmid = vmid;

	r = adev->mes.funcs->reset_hw_queue(&adev->mes, &queue_input);

	if (r)

		DRM_ERROR("failed to reset hardware queue by mmio, queue id = %d\n",

			  queue_id);

	return r;

}



int amdgpu_mes_map_legacy_queue(struct amdgpu_device *adev,

				struct amdgpu_ring *ring)

{

drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h

+0 −19
Original line number Diff line number Diff line
@@ -235,18 +235,6 @@ struct mes_remove_queue_input { 
	uint64_t	gang_context_addr;

};



struct mes_reset_queue_input {

	uint32_t	doorbell_offset;

	uint64_t	gang_context_addr;

	bool		use_mmio;

	uint32_t	queue_type;

	uint32_t	me_id;

	uint32_t	pipe_id;

	uint32_t	queue_id;

	uint32_t	xcc_id;

	uint32_t	vmid;

};



struct mes_map_legacy_queue_input {

	uint32_t                           queue_type;

	uint32_t                           doorbell_offset;
@@ -377,9 +365,6 @@ struct amdgpu_mes_funcs { 


	int (*reset_legacy_queue)(struct amdgpu_mes *mes,

				  struct mes_reset_legacy_queue_input *input);



	int (*reset_hw_queue)(struct amdgpu_mes *mes,

			      struct mes_reset_queue_input *input);

};



#define amdgpu_mes_kiq_hw_init(adev) (adev)->mes.kiq_hw_init((adev))
@@ -394,10 +379,6 @@ void amdgpu_mes_fini(struct amdgpu_device *adev); 
int amdgpu_mes_suspend(struct amdgpu_device *adev);

int amdgpu_mes_resume(struct amdgpu_device *adev);



int amdgpu_mes_reset_hw_queue(struct amdgpu_device *adev, int queue_id);

int amdgpu_mes_reset_hw_queue_mmio(struct amdgpu_device *adev, int queue_type,

				   int me_id, int pipe_id, int queue_id, int vmid);



int amdgpu_mes_map_legacy_queue(struct amdgpu_device *adev,

				struct amdgpu_ring *ring);

int amdgpu_mes_unmap_legacy_queue(struct amdgpu_device *adev,

drivers/gpu/drm/amd/amdgpu/mes_v11_0.c

+0 −26
Original line number Diff line number Diff line
@@ -475,31 +475,6 @@ static int mes_v11_0_reset_queue_mmio(struct amdgpu_mes *mes, uint32_t queue_typ 
	return r;

}



static int mes_v11_0_reset_hw_queue(struct amdgpu_mes *mes,

				    struct mes_reset_queue_input *input)

{

	if (input->use_mmio)

		return mes_v11_0_reset_queue_mmio(mes, input->queue_type,

						  input->me_id, input->pipe_id,

						  input->queue_id, input->vmid);



	union MESAPI__RESET mes_reset_queue_pkt;



	memset(&mes_reset_queue_pkt, 0, sizeof(mes_reset_queue_pkt));



	mes_reset_queue_pkt.header.type = MES_API_TYPE_SCHEDULER;

	mes_reset_queue_pkt.header.opcode = MES_SCH_API_RESET;

	mes_reset_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;



	mes_reset_queue_pkt.doorbell_offset = input->doorbell_offset;

	mes_reset_queue_pkt.gang_context_addr = input->gang_context_addr;

	/*mes_reset_queue_pkt.reset_queue_only = 1;*/



	return mes_v11_0_submit_pkt_and_poll_completion(mes,

			&mes_reset_queue_pkt, sizeof(mes_reset_queue_pkt),

			offsetof(union MESAPI__RESET, api_status));

}



static int mes_v11_0_map_legacy_queue(struct amdgpu_mes *mes,

				      struct mes_map_legacy_queue_input *input)

{
@@ -817,7 +792,6 @@ static const struct amdgpu_mes_funcs mes_v11_0_funcs = { 
	.resume_gang = mes_v11_0_resume_gang,

	.misc_op = mes_v11_0_misc_op,

	.reset_legacy_queue = mes_v11_0_reset_legacy_queue,

	.reset_hw_queue = mes_v11_0_reset_hw_queue,

};



static int mes_v11_0_allocate_ucode_buffer(struct amdgpu_device *adev,

drivers/gpu/drm/amd/amdgpu/mes_v12_0.c

+0 −27
Original line number Diff line number Diff line
@@ -494,32 +494,6 @@ static int mes_v12_0_reset_queue_mmio(struct amdgpu_mes *mes, uint32_t queue_typ 
	return r;

}



static int mes_v12_0_reset_hw_queue(struct amdgpu_mes *mes,

				    struct mes_reset_queue_input *input)

{

	union MESAPI__RESET mes_reset_queue_pkt;

	int pipe;



	memset(&mes_reset_queue_pkt, 0, sizeof(mes_reset_queue_pkt));



	mes_reset_queue_pkt.header.type = MES_API_TYPE_SCHEDULER;

	mes_reset_queue_pkt.header.opcode = MES_SCH_API_RESET;

	mes_reset_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;



	mes_reset_queue_pkt.doorbell_offset = input->doorbell_offset;

	mes_reset_queue_pkt.gang_context_addr = input->gang_context_addr;

	/*mes_reset_queue_pkt.reset_queue_only = 1;*/



	if (mes->adev->enable_uni_mes)

		pipe = AMDGPU_MES_KIQ_PIPE;

	else

		pipe = AMDGPU_MES_SCHED_PIPE;



	return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe,

			&mes_reset_queue_pkt, sizeof(mes_reset_queue_pkt),

			offsetof(union MESAPI__RESET, api_status));

}



static int mes_v12_0_map_legacy_queue(struct amdgpu_mes *mes,

				      struct mes_map_legacy_queue_input *input)

{
@@ -914,7 +888,6 @@ static const struct amdgpu_mes_funcs mes_v12_0_funcs = { 
	.resume_gang = mes_v12_0_resume_gang,

	.misc_op = mes_v12_0_misc_op,

	.reset_legacy_queue = mes_v12_0_reset_legacy_queue,

	.reset_hw_queue = mes_v12_0_reset_hw_queue,

};



static int mes_v12_0_allocate_ucode_buffer(struct amdgpu_device *adev,