Commit 66122616 authored by Ahmed S. Darwish's avatar Ahmed S. Darwish Committed by Ingo Molnar
Browse files

x86/cacheinfo: Separate Intel CPUID leaf 0x4 handling 



init_intel_cacheinfo() was overly complex.  It parsed leaf 0x4 data,
leaf 0x2 data, and performed post-processing, all within one function.
Parent commit moved leaf 0x2 parsing and the post-processing logic into
their own functions.

Continue the refactoring by extracting leaf 0x4 parsing into its own
function.  Initialize local L2/L3 topology ID variables to BAD_APICID by
default, thus ensuring they can be used unconditionally.

Suggested-by: default avatarThomas Gleixner <tglx@linutronix.de>
Signed-off-by: default avatarAhmed S. Darwish <darwi@linutronix.de>
Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Link: https://lore.kernel.org/r/20250324133324.23458-25-darwi@linutronix.de
parent 5adfd367

arch/x86/kernel/cpu/cacheinfo.c

+54 −56
Original line number Diff line number Diff line
@@ -400,31 +400,32 @@ static void intel_cacheinfo_0x2(struct cpuinfo_x86 *c) 
	intel_cacheinfo_done(c, l3, l2, l1i, l1d);

}



void init_intel_cacheinfo(struct cpuinfo_x86 *c)

static bool intel_cacheinfo_0x4(struct cpuinfo_x86 *c)

{

	struct cpu_cacheinfo *ci = get_cpu_cacheinfo(c->cpu_index);

	unsigned int l1i = 0, l1d = 0, l2 = 0, l3 = 0;

	unsigned int l2_id = 0, l3_id = 0;

	unsigned int l2_id = BAD_APICID, l3_id = BAD_APICID;

	unsigned int l1d = 0, l1i = 0, l2 = 0, l3 = 0;



	if (c->cpuid_level < 4)

		return false;



	if (c->cpuid_level > 3) {

	/*

	 * There should be at least one leaf. A non-zero value means

		 * that the number of leaves has been initialized.

	 * that the number of leaves has been previously initialized.

	 */

	if (!ci->num_leaves)

		ci->num_leaves = find_num_cache_leaves(c);



		/*

		 * Whenever possible use cpuid(4), deterministic cache

		 * parameters cpuid leaf to find the cache details

		 */

	if (!ci->num_leaves)

		return false;



	for (int i = 0; i < ci->num_leaves; i++) {

		unsigned int num_threads_sharing, index_msb;

		struct _cpuid4_info id4 = {};

			int retval;

		int ret;



			retval = intel_fill_cpuid4_info(i, &id4);

			if (retval < 0)

		ret = intel_fill_cpuid4_info(i, &id4);

		if (ret < 0)

			continue;



		switch (id4.eax.split.level) {
@@ -450,23 +451,20 @@ void init_intel_cacheinfo(struct cpuinfo_x86 *c) 
			break;

		}

	}

	}



	/* Don't use CPUID(2) if CPUID(4) is supported. */

	if (!ci->num_leaves && c->cpuid_level > 1) {

		intel_cacheinfo_0x2(c);

		return;

	}



	if (l2) {

		c->topo.llc_id = l2_id;

	c->topo.l2c_id = l2_id;

	c->topo.llc_id = (l3_id == BAD_APICID) ? l2_id : l3_id;

	intel_cacheinfo_done(c, l3, l2, l1i, l1d);

	return true;

}



	if (l3)

		c->topo.llc_id = l3_id;

void init_intel_cacheinfo(struct cpuinfo_x86 *c)

{

	/* Don't use CPUID(2) if CPUID(4) is supported. */

	if (intel_cacheinfo_0x4(c))

		return;



	intel_cacheinfo_done(c, l3, l2, l1i, l1d);

	intel_cacheinfo_0x2(c);

}



static int __cache_amd_cpumap_setup(unsigned int cpu, int index,