Commit 661a8689 authored by Russell King (Oracle)'s avatar Russell King (Oracle) Committed by Jakub Kicinski
Browse files

net: stmmac: mdio: move initialisation of priv->clk_csr to stmmac_mdio 



The only user of priv->clk_csr is the MDIO code, so move its
initialisation to stmmac_mdio.c.

Signed-off-by: default avatarRussell King (Oracle) <rmk+kernel@armlinux.org.uk>
Reviewed-by: default avatarAndrew Lunn <andrew@lunn.ch>
Tested-by: default avatarMohd Ayaan Anwar <quic_mohdayaa@quicinc.com>
Link: https://patch.msgid.link/E1uu8oR-00000001vpB-3fbY@rmk-PC.armlinux.org.uk


Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parent 3581acbb

drivers/net/ethernet/stmicro/stmmac/stmmac_main.c

+0 −82
Original line number Diff line number Diff line
@@ -314,77 +314,6 @@ static void stmmac_global_err(struct stmmac_priv *priv) 
	stmmac_service_event_schedule(priv);

}



/**

 * stmmac_clk_csr_set - dynamically set the MDC clock

 * @priv: driver private structure

 * Description: this is to dynamically set the MDC clock according to the csr

 * clock input.

 * Note:

 *	If a specific clk_csr value is passed from the platform

 *	this means that the CSR Clock Range selection cannot be

 *	changed at run-time and it is fixed (as reported in the driver

 *	documentation). Viceversa the driver will try to set the MDC

 *	clock dynamically according to the actual clock input.

 */

static void stmmac_clk_csr_set(struct stmmac_priv *priv)

{

	unsigned long clk_rate;



	clk_rate = clk_get_rate(priv->plat->stmmac_clk);



	/* Platform provided default clk_csr would be assumed valid

	 * for all other cases except for the below mentioned ones.

	 * For values higher than the IEEE 802.3 specified frequency

	 * we can not estimate the proper divider as it is not known

	 * the frequency of clk_csr_i. So we do not change the default

	 * divider.

	 */

	if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) {

		if (clk_rate < CSR_F_35M)

			priv->clk_csr = STMMAC_CSR_20_35M;

		else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M))

			priv->clk_csr = STMMAC_CSR_35_60M;

		else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M))

			priv->clk_csr = STMMAC_CSR_60_100M;

		else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M))

			priv->clk_csr = STMMAC_CSR_100_150M;

		else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M))

			priv->clk_csr = STMMAC_CSR_150_250M;

		else if ((clk_rate >= CSR_F_250M) && (clk_rate <= CSR_F_300M))

			priv->clk_csr = STMMAC_CSR_250_300M;

		else if ((clk_rate >= CSR_F_300M) && (clk_rate < CSR_F_500M))

			priv->clk_csr = STMMAC_CSR_300_500M;

		else if ((clk_rate >= CSR_F_500M) && (clk_rate < CSR_F_800M))

			priv->clk_csr = STMMAC_CSR_500_800M;

	}



	if (priv->plat->flags & STMMAC_FLAG_HAS_SUN8I) {

		if (clk_rate > 160000000)

			priv->clk_csr = 0x03;

		else if (clk_rate > 80000000)

			priv->clk_csr = 0x02;

		else if (clk_rate > 40000000)

			priv->clk_csr = 0x01;

		else

			priv->clk_csr = 0;

	}



	if (priv->plat->has_xgmac) {

		if (clk_rate > 400000000)

			priv->clk_csr = 0x5;

		else if (clk_rate > 350000000)

			priv->clk_csr = 0x4;

		else if (clk_rate > 300000000)

			priv->clk_csr = 0x3;

		else if (clk_rate > 250000000)

			priv->clk_csr = 0x2;

		else if (clk_rate > 150000000)

			priv->clk_csr = 0x1;

		else

			priv->clk_csr = 0x0;

	}

}



static void print_pkt(unsigned char *buf, int len)

{

	pr_debug("len = %d byte, buf addr: 0x%p\n", len, buf);
@@ -7718,17 +7647,6 @@ int stmmac_dvr_probe(struct device *device, 


	stmmac_fpe_init(priv);



	/* If a specific clk_csr value is passed from the platform

	 * this means that the CSR Clock Range selection cannot be

	 * changed at run-time and it is fixed. Viceversa the driver'll try to

	 * set the MDC clock dynamically according to the csr actual

	 * clock input.

	 */

	if (priv->plat->clk_csr >= 0)

		priv->clk_csr = priv->plat->clk_csr;

	else

		stmmac_clk_csr_set(priv);



	stmmac_check_pcs_mode(priv);



	pm_runtime_get_noresume(device);

drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c

+86 −2
Original line number Diff line number Diff line
@@ -473,8 +473,92 @@ void stmmac_pcs_clean(struct net_device *ndev) 
	priv->hw->xpcs = NULL;

}



static void stmmac_mdio_bus_config(struct stmmac_priv *priv, u32 value)

/**

 * stmmac_clk_csr_set - dynamically set the MDC clock

 * @priv: driver private structure

 * Description: this is to dynamically set the MDC clock according to the csr

 * clock input.

 * Note:

 *	If a specific clk_csr value is passed from the platform

 *	this means that the CSR Clock Range selection cannot be

 *	changed at run-time and it is fixed (as reported in the driver

 *	documentation). Viceversa the driver will try to set the MDC

 *	clock dynamically according to the actual clock input.

 */

static void stmmac_clk_csr_set(struct stmmac_priv *priv)

{

	unsigned long clk_rate;



	clk_rate = clk_get_rate(priv->plat->stmmac_clk);



	/* Platform provided default clk_csr would be assumed valid

	 * for all other cases except for the below mentioned ones.

	 * For values higher than the IEEE 802.3 specified frequency

	 * we can not estimate the proper divider as it is not known

	 * the frequency of clk_csr_i. So we do not change the default

	 * divider.

	 */

	if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) {

		if (clk_rate < CSR_F_35M)

			priv->clk_csr = STMMAC_CSR_20_35M;

		else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M))

			priv->clk_csr = STMMAC_CSR_35_60M;

		else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M))

			priv->clk_csr = STMMAC_CSR_60_100M;

		else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M))

			priv->clk_csr = STMMAC_CSR_100_150M;

		else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M))

			priv->clk_csr = STMMAC_CSR_150_250M;

		else if ((clk_rate >= CSR_F_250M) && (clk_rate <= CSR_F_300M))

			priv->clk_csr = STMMAC_CSR_250_300M;

		else if ((clk_rate >= CSR_F_300M) && (clk_rate < CSR_F_500M))

			priv->clk_csr = STMMAC_CSR_300_500M;

		else if ((clk_rate >= CSR_F_500M) && (clk_rate < CSR_F_800M))

			priv->clk_csr = STMMAC_CSR_500_800M;

	}



	if (priv->plat->flags & STMMAC_FLAG_HAS_SUN8I) {

		if (clk_rate > 160000000)

			priv->clk_csr = 0x03;

		else if (clk_rate > 80000000)

			priv->clk_csr = 0x02;

		else if (clk_rate > 40000000)

			priv->clk_csr = 0x01;

		else

			priv->clk_csr = 0;

	}



	if (priv->plat->has_xgmac) {

		if (clk_rate > 400000000)

			priv->clk_csr = 0x5;

		else if (clk_rate > 350000000)

			priv->clk_csr = 0x4;

		else if (clk_rate > 300000000)

			priv->clk_csr = 0x3;

		else if (clk_rate > 250000000)

			priv->clk_csr = 0x2;

		else if (clk_rate > 150000000)

			priv->clk_csr = 0x1;

		else

			priv->clk_csr = 0x0;

	}

}



static void stmmac_mdio_bus_config(struct stmmac_priv *priv)

{

	u32 value;



	/* If a specific clk_csr value is passed from the platform, this means

	 * that the CSR Clock Range value should not be computed from the CSR

	 * clock.

	 */

	if (priv->plat->clk_csr >= 0) {

		value = priv->plat->clk_csr;

	} else {

		stmmac_clk_csr_set(priv);

		value = priv->clk_csr;

	}



	value <<= priv->hw->mii.clk_csr_shift;



	if (value & ~priv->hw->mii.clk_csr_mask)
@@ -505,7 +589,7 @@ int stmmac_mdio_register(struct net_device *ndev) 
	if (!mdio_bus_data)

		return 0;



	stmmac_mdio_bus_config(priv, priv->clk_csr);

	stmmac_mdio_bus_config(priv);



	new_bus = mdiobus_alloc();

	if (!new_bus)