Loading arch/powerpc/kernel/misc.S +0 −52 Original line number Diff line number Diff line Loading @@ -86,58 +86,6 @@ _GLOBAL(_outsb) sync blr _GLOBAL(_insw) sync cmpwi 0,r5,0 mtctr r5 subi r4,r4,2 blelr- 00: lhbrx r5,0,r3 eieio sthu r5,2(r4) bdnz 00b twi 0,r5,0 isync blr _GLOBAL(_outsw) cmpwi 0,r5,0 mtctr r5 subi r4,r4,2 blelr- sync 00: lhzu r5,2(r4) sthbrx r5,0,r3 bdnz 00b sync blr _GLOBAL(_insl) sync cmpwi 0,r5,0 mtctr r5 subi r4,r4,4 blelr- 00: lwbrx r5,0,r3 eieio stwu r5,4(r4) bdnz 00b twi 0,r5,0 isync blr _GLOBAL(_outsl) cmpwi 0,r5,0 mtctr r5 subi r4,r4,4 blelr- sync 00: lwzu r5,4(r4) stwbrx r5,0,r3 bdnz 00b sync blr #ifdef CONFIG_PPC32 _GLOBAL(__ide_mm_insw) #endif Loading arch/powerpc/kernel/ppc_ksyms.c +0 −4 Original line number Diff line number Diff line Loading @@ -104,10 +104,6 @@ EXPORT_SYMBOL(__ide_mm_outsl); EXPORT_SYMBOL(_insb); EXPORT_SYMBOL(_outsb); EXPORT_SYMBOL(_insw); EXPORT_SYMBOL(_outsw); EXPORT_SYMBOL(_insl); EXPORT_SYMBOL(_outsl); EXPORT_SYMBOL(_insw_ns); EXPORT_SYMBOL(_outsw_ns); EXPORT_SYMBOL(_insl_ns); Loading arch/ppc/kernel/misc.S +0 −84 Original line number Diff line number Diff line Loading @@ -768,90 +768,6 @@ _GLOBAL(_outsb) bdnz 00b blr _GLOBAL(_insw) cmpwi 0,r5,0 mtctr r5 subi r4,r4,2 blelr- 00: lhbrx r5,0,r3 01: eieio 02: sthu r5,2(r4) ISYNC_8xx .section .fixup,"ax" 03: blr .text .section __ex_table, "a" .align 2 .long 00b, 03b .long 01b, 03b .long 02b, 03b .text bdnz 00b blr _GLOBAL(_outsw) cmpwi 0,r5,0 mtctr r5 subi r4,r4,2 blelr- 00: lhzu r5,2(r4) 01: eieio 02: sthbrx r5,0,r3 ISYNC_8xx .section .fixup,"ax" 03: blr .text .section __ex_table, "a" .align 2 .long 00b, 03b .long 01b, 03b .long 02b, 03b .text bdnz 00b blr _GLOBAL(_insl) cmpwi 0,r5,0 mtctr r5 subi r4,r4,4 blelr- 00: lwbrx r5,0,r3 01: eieio 02: stwu r5,4(r4) ISYNC_8xx .section .fixup,"ax" 03: blr .text .section __ex_table, "a" .align 2 .long 00b, 03b .long 01b, 03b .long 02b, 03b .text bdnz 00b blr _GLOBAL(_outsl) cmpwi 0,r5,0 mtctr r5 subi r4,r4,4 blelr- 00: lwzu r5,4(r4) 01: stwbrx r5,0,r3 02: eieio ISYNC_8xx .section .fixup,"ax" 03: blr .text .section __ex_table, "a" .align 2 .long 00b, 03b .long 01b, 03b .long 02b, 03b .text bdnz 00b blr _GLOBAL(__ide_mm_insw) _GLOBAL(_insw_ns) cmpwi 0,r5,0 Loading arch/ppc/kernel/ppc_ksyms.c +0 −4 Original line number Diff line number Diff line Loading @@ -122,10 +122,6 @@ EXPORT_SYMBOL(__ide_mm_outsl); EXPORT_SYMBOL(_insb); EXPORT_SYMBOL(_outsb); EXPORT_SYMBOL(_insw); EXPORT_SYMBOL(_outsw); EXPORT_SYMBOL(_insl); EXPORT_SYMBOL(_outsl); EXPORT_SYMBOL(_insw_ns); EXPORT_SYMBOL(_outsw_ns); EXPORT_SYMBOL(_insl_ns); Loading include/asm-powerpc/io.h +0 −4 Original line number Diff line number Diff line Loading @@ -151,10 +151,6 @@ static inline void __raw_writeq(unsigned long v, volatile void __iomem *addr) extern void _insb(volatile u8 __iomem *port, void *buf, int ns); extern void _outsb(volatile u8 __iomem *port, const void *buf, int ns); extern void _insw(volatile u16 __iomem *port, void *buf, int ns); extern void _outsw(volatile u16 __iomem *port, const void *buf, int ns); extern void _insl(volatile u32 __iomem *port, void *buf, int nl); extern void _outsl(volatile u32 __iomem *port, const void *buf, int nl); extern void _insw_ns(volatile u16 __iomem *port, void *buf, int ns); extern void _outsw_ns(volatile u16 __iomem *port, const void *buf, int ns); extern void _insl_ns(volatile u32 __iomem *port, void *buf, int nl); Loading Loading
arch/powerpc/kernel/misc.S +0 −52 Original line number Diff line number Diff line Loading @@ -86,58 +86,6 @@ _GLOBAL(_outsb) sync blr _GLOBAL(_insw) sync cmpwi 0,r5,0 mtctr r5 subi r4,r4,2 blelr- 00: lhbrx r5,0,r3 eieio sthu r5,2(r4) bdnz 00b twi 0,r5,0 isync blr _GLOBAL(_outsw) cmpwi 0,r5,0 mtctr r5 subi r4,r4,2 blelr- sync 00: lhzu r5,2(r4) sthbrx r5,0,r3 bdnz 00b sync blr _GLOBAL(_insl) sync cmpwi 0,r5,0 mtctr r5 subi r4,r4,4 blelr- 00: lwbrx r5,0,r3 eieio stwu r5,4(r4) bdnz 00b twi 0,r5,0 isync blr _GLOBAL(_outsl) cmpwi 0,r5,0 mtctr r5 subi r4,r4,4 blelr- sync 00: lwzu r5,4(r4) stwbrx r5,0,r3 bdnz 00b sync blr #ifdef CONFIG_PPC32 _GLOBAL(__ide_mm_insw) #endif Loading
arch/powerpc/kernel/ppc_ksyms.c +0 −4 Original line number Diff line number Diff line Loading @@ -104,10 +104,6 @@ EXPORT_SYMBOL(__ide_mm_outsl); EXPORT_SYMBOL(_insb); EXPORT_SYMBOL(_outsb); EXPORT_SYMBOL(_insw); EXPORT_SYMBOL(_outsw); EXPORT_SYMBOL(_insl); EXPORT_SYMBOL(_outsl); EXPORT_SYMBOL(_insw_ns); EXPORT_SYMBOL(_outsw_ns); EXPORT_SYMBOL(_insl_ns); Loading
arch/ppc/kernel/misc.S +0 −84 Original line number Diff line number Diff line Loading @@ -768,90 +768,6 @@ _GLOBAL(_outsb) bdnz 00b blr _GLOBAL(_insw) cmpwi 0,r5,0 mtctr r5 subi r4,r4,2 blelr- 00: lhbrx r5,0,r3 01: eieio 02: sthu r5,2(r4) ISYNC_8xx .section .fixup,"ax" 03: blr .text .section __ex_table, "a" .align 2 .long 00b, 03b .long 01b, 03b .long 02b, 03b .text bdnz 00b blr _GLOBAL(_outsw) cmpwi 0,r5,0 mtctr r5 subi r4,r4,2 blelr- 00: lhzu r5,2(r4) 01: eieio 02: sthbrx r5,0,r3 ISYNC_8xx .section .fixup,"ax" 03: blr .text .section __ex_table, "a" .align 2 .long 00b, 03b .long 01b, 03b .long 02b, 03b .text bdnz 00b blr _GLOBAL(_insl) cmpwi 0,r5,0 mtctr r5 subi r4,r4,4 blelr- 00: lwbrx r5,0,r3 01: eieio 02: stwu r5,4(r4) ISYNC_8xx .section .fixup,"ax" 03: blr .text .section __ex_table, "a" .align 2 .long 00b, 03b .long 01b, 03b .long 02b, 03b .text bdnz 00b blr _GLOBAL(_outsl) cmpwi 0,r5,0 mtctr r5 subi r4,r4,4 blelr- 00: lwzu r5,4(r4) 01: stwbrx r5,0,r3 02: eieio ISYNC_8xx .section .fixup,"ax" 03: blr .text .section __ex_table, "a" .align 2 .long 00b, 03b .long 01b, 03b .long 02b, 03b .text bdnz 00b blr _GLOBAL(__ide_mm_insw) _GLOBAL(_insw_ns) cmpwi 0,r5,0 Loading
arch/ppc/kernel/ppc_ksyms.c +0 −4 Original line number Diff line number Diff line Loading @@ -122,10 +122,6 @@ EXPORT_SYMBOL(__ide_mm_outsl); EXPORT_SYMBOL(_insb); EXPORT_SYMBOL(_outsb); EXPORT_SYMBOL(_insw); EXPORT_SYMBOL(_outsw); EXPORT_SYMBOL(_insl); EXPORT_SYMBOL(_outsl); EXPORT_SYMBOL(_insw_ns); EXPORT_SYMBOL(_outsw_ns); EXPORT_SYMBOL(_insl_ns); Loading
include/asm-powerpc/io.h +0 −4 Original line number Diff line number Diff line Loading @@ -151,10 +151,6 @@ static inline void __raw_writeq(unsigned long v, volatile void __iomem *addr) extern void _insb(volatile u8 __iomem *port, void *buf, int ns); extern void _outsb(volatile u8 __iomem *port, const void *buf, int ns); extern void _insw(volatile u16 __iomem *port, void *buf, int ns); extern void _outsw(volatile u16 __iomem *port, const void *buf, int ns); extern void _insl(volatile u32 __iomem *port, void *buf, int nl); extern void _outsl(volatile u32 __iomem *port, const void *buf, int nl); extern void _insw_ns(volatile u16 __iomem *port, void *buf, int ns); extern void _outsw_ns(volatile u16 __iomem *port, const void *buf, int ns); extern void _insl_ns(volatile u32 __iomem *port, void *buf, int nl); Loading