Commit 662a601a authored by Anup Patel's avatar Anup Patel Committed by Anup Patel
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RISC-V: Detect Zicond from ISA string 



The RISC-V integer conditional (Zicond) operation extension defines
standard conditional arithmetic and conditional-select/move operations
which are inspired from the XVentanaCondOps extension. In fact, QEMU
RISC-V also has support for emulating Zicond extension.

Let us detect Zicond extension from ISA string available through
DT or ACPI.

Signed-off-by: default avatarAnup Patel <apatel@ventanamicro.com>
Reviewed-by: default avatarAndrew Jones <ajones@ventanamicro.com>
Reviewed-by: default avatarConor Dooley <conor.dooley@microchip.com>
Acked-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: default avatarAnup Patel <anup@brainfault.org>
parent a4f5f398

arch/riscv/include/asm/hwcap.h

+1 −0
Original line number Diff line number Diff line
@@ -59,6 +59,7 @@ 
#define RISCV_ISA_EXT_ZIFENCEI		41

#define RISCV_ISA_EXT_ZIHPM		42

#define RISCV_ISA_EXT_SMSTATEEN		43

#define RISCV_ISA_EXT_ZICOND		44



#define RISCV_ISA_EXT_MAX		64

arch/riscv/kernel/cpufeature.c

+1 −0
Original line number Diff line number Diff line
@@ -167,6 +167,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { 
	__RISCV_ISA_EXT_DATA(zicbom, RISCV_ISA_EXT_ZICBOM),

	__RISCV_ISA_EXT_DATA(zicboz, RISCV_ISA_EXT_ZICBOZ),

	__RISCV_ISA_EXT_DATA(zicntr, RISCV_ISA_EXT_ZICNTR),

	__RISCV_ISA_EXT_DATA(zicond, RISCV_ISA_EXT_ZICOND),

	__RISCV_ISA_EXT_DATA(zicsr, RISCV_ISA_EXT_ZICSR),

	__RISCV_ISA_EXT_DATA(zifencei, RISCV_ISA_EXT_ZIFENCEI),

	__RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE),