Unverified Commit 662f9ddc authored by Jia Yao's avatar Jia Yao Committed by Rodrigo Vivi
Browse files

drm/xe/uapi: Reject coh_none PAT index for CPU_ADDR_MIRROR 



Add validation in xe_vm_bind_ioctl() to reject PAT indices
with XE_COH_NONE coherency mode when used with
DRM_XE_VM_BIND_FLAG_CPU_ADDR_MIRROR.

CPU address mirror mappings use system memory that is CPU
cached, which makes them incompatible with COH_NONE PAT
indices. Allowing COH_NONE with CPU cached buffers is a
security risk, as the GPU may bypass CPU caches and read
stale sensitive data from DRAM.

Although CPU_ADDR_MIRROR does not create an immediate
mapping, the backing system memory is still CPU cached.
Apply the same PAT coherency restrictions as
DRM_XE_VM_BIND_OP_MAP_USERPTR.

v2:
- Correct fix tag

v6:
- No change

v7:
- Correct fix tag

v8:
- Rebase

v9:
- Limit the restrictions to iGPU

v10:
- Just add the iGPU logic but keep dGPU logic

Fixes: b43e864a ("drm/xe/uapi: Add DRM_XE_VM_BIND_FLAG_CPU_ADDR_MIRROR")
Cc: <stable@vger.kernel.org> # v6.15+
Cc: Shuicheng Lin <shuicheng.lin@intel.com>
Cc: Mathew Alwin <alwin.mathew@intel.com>
Cc: Michal Mrozek <michal.mrozek@intel.com>
Cc: Matthew Brost <matthew.brost@intel.com>
Cc: Matthew Auld <matthew.auld@intel.com>
Signed-off-by: default avatarJia Yao <jia.yao@intel.com>
Reviewed-by: default avatarMatthew Auld <matthew.auld@intel.com>
Acked-by: default avatarMichal Mrozek <michal.mrozek@intel.com>
Signed-off-by: default avatarMatthew Auld <matthew.auld@intel.com>
Link: https://patch.msgid.link/20260417055917.2027459-3-jia.yao@intel.com


(cherry picked from commit 4d58d7535e826a3175527b6174502f0db319d7f6)
Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
parent 4e5591c2

drivers/gpu/drm/xe/xe_vm.c

+2 −0
Original line number Diff line number Diff line
@@ -3658,6 +3658,8 @@ static int vm_bind_ioctl_check_args(struct xe_device *xe, struct xe_vm *vm, 
				 op == DRM_XE_VM_BIND_OP_MAP_USERPTR) ||

		    XE_IOCTL_DBG(xe, coh_mode == XE_COH_NONE &&

				 op == DRM_XE_VM_BIND_OP_MAP_USERPTR) ||

		    XE_IOCTL_DBG(xe, !IS_DGFX(xe) && coh_mode == XE_COH_NONE &&

				 is_cpu_addr_mirror) ||

		    XE_IOCTL_DBG(xe, xe_device_is_l2_flush_optimized(xe) &&

				 (op == DRM_XE_VM_BIND_OP_MAP_USERPTR ||

				  is_cpu_addr_mirror) &&