Commit 66a1b7e0 authored by Karol Kolacinski's avatar Karol Kolacinski Committed by Paolo Abeni
Browse files

ice: Refactor E825C PHY registers info struct 



Simplify ice_phy_reg_info_eth56g struct definition to include base
address for the very first quad. Use base address info and 'step'
value to determine address for specific PHY quad.

Reviewed-by: default avatarPrzemek Kitszel <przemyslaw.kitszel@intel.com>
Signed-off-by: default avatarKarol Kolacinski <karol.kolacinski@intel.com>
Signed-off-by: default avatarGrzegorz Nitka <grzegorz.nitka@intel.com>
Reviewed-by: default avatarSimon Horman <horms@kernel.org>
Tested-by: Rinitha S <sx.rinitha@intel.com> (A Contingent worker at Intel)
Signed-off-by: default avatarTony Nguyen <anthony.l.nguyen@intel.com>
Link: https://patch.msgid.link/20250310174502.3708121-4-anthony.l.nguyen@intel.com


Signed-off-by: default avatarPaolo Abeni <pabeni@redhat.com>
parent 178edd26

drivers/net/ethernet/intel/ice/ice_ptp_consts.h

+15 −60
Original line number Diff line number Diff line
@@ -10,70 +10,25 @@ 
/* Constants defined for the PTP 1588 clock hardware. */



const struct ice_phy_reg_info_eth56g eth56g_phy_res[NUM_ETH56G_PHY_RES] = {

	/* ETH56G_PHY_REG_PTP */

	{

		/* base_addr */

		{

			0x092000,

			0x126000,

			0x1BA000,

			0x24E000,

			0x2E2000,

		},

		/* step */

		0x98,

	},

	/* ETH56G_PHY_MEM_PTP */

	{

		/* base_addr */

		{

			0x093000,

			0x127000,

			0x1BB000,

			0x24F000,

			0x2E3000,

		},

		/* step */

		0x200,

	[ETH56G_PHY_REG_PTP] = {

		.base_addr = 0x092000,

		.step = 0x98,

	},

	/* ETH56G_PHY_REG_XPCS */

	{

		/* base_addr */

		{

			0x000000,

			0x009400,

			0x128000,

			0x1BC000,

			0x250000,

	[ETH56G_PHY_MEM_PTP] = {

		.base_addr = 0x093000,

		.step = 0x200,

	},

		/* step */

		0x21000,

	[ETH56G_PHY_REG_XPCS] = {

		.base_addr = 0x000000,

		.step = 0x21000,

	},

	/* ETH56G_PHY_REG_MAC */

	{

		/* base_addr */

		{

			0x085000,

			0x119000,

			0x1AD000,

			0x241000,

			0x2D5000,

	[ETH56G_PHY_REG_MAC] = {

		.base_addr = 0x085000,

		.step = 0x1000,

	},

		/* step */

		0x1000,

	},

	/* ETH56G_PHY_REG_GPCS */

	{

		/* base_addr */

		{

			0x084000,

			0x118000,

			0x1AC000,

			0x240000,

			0x2D4000,

		},

		/* step */

		0x400,

	[ETH56G_PHY_REG_GPCS] = {

		.base_addr = 0x084000,

		.step = 0x400,

	},

};

drivers/net/ethernet/intel/ice/ice_ptp_hw.c

+3 −3
Original line number Diff line number Diff line
@@ -1010,7 +1010,7 @@ static int ice_phy_res_address_eth56g(struct ice_hw *hw, u8 lane, 


	/* Lanes 4..7 are in fact 0..3 on a second PHY */

	lane %= hw->ptp.ports_per_phy;

	*addr = eth56g_phy_res[res_type].base[0] +

	*addr = eth56g_phy_res[res_type].base_addr +

		lane * eth56g_phy_res[res_type].step + offset;



	return 0;
@@ -1240,7 +1240,7 @@ static int ice_write_quad_ptp_reg_eth56g(struct ice_hw *hw, u8 port, 
	if (port >= hw->ptp.num_lports)

		return -EIO;



	addr = eth56g_phy_res[ETH56G_PHY_REG_PTP].base[0] + offset;

	addr = eth56g_phy_res[ETH56G_PHY_REG_PTP].base_addr + offset;



	return ice_write_phy_eth56g(hw, port, addr, val);

}
@@ -1265,7 +1265,7 @@ static int ice_read_quad_ptp_reg_eth56g(struct ice_hw *hw, u8 port, 
	if (port >= hw->ptp.num_lports)

		return -EIO;



	addr = eth56g_phy_res[ETH56G_PHY_REG_PTP].base[0] + offset;

	addr = eth56g_phy_res[ETH56G_PHY_REG_PTP].base_addr + offset;



	return ice_read_phy_eth56g(hw, port, addr, val);

}

drivers/net/ethernet/intel/ice/ice_ptp_hw.h

+2 −2
Original line number Diff line number Diff line
@@ -65,14 +65,14 @@ enum ice_eth56g_link_spd { 


/**

 * struct ice_phy_reg_info_eth56g - ETH56G PHY register parameters

 * @base: base address for each PHY block

 * @base_addr: base address for each PHY block

 * @step: step between PHY lanes

 *

 * Characteristic information for the various PHY register parameters in the

 * ETH56G devices

 */

struct ice_phy_reg_info_eth56g {

	u32 base[NUM_ETH56G_PHY_RES];

	u32 base_addr;

	u32 step;

};