Commit 66d76b6d authored by Cristian Ciocaltea's avatar Cristian Ciocaltea Committed by Vinod Koul
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phy: rockchip: samsung-hdptx: Drop hw_rate driver data 



The ->hw_rate member of struct rk_hdptx_phy was mainly used to keep
track of the clock rate programmed in hardware and support implementing
the ->recalc_rate() callback in hdptx_phy_clk_ops.

Computing the clock rate from the actual PHY PLL configuration seems to
work reliably, hence remove the now redundant struct member.

Signed-off-by: default avatarCristian Ciocaltea <cristian.ciocaltea@collabora.com>
Link: https://patch.msgid.link/20260113-phy-hdptx-frl-v6-8-8d5f97419c0b@collabora.com


Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent 3481fc04

drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c

+2 −11
Original line number Diff line number Diff line
@@ -387,7 +387,6 @@ struct rk_hdptx_phy { 


	/* clk provider */

	struct clk_hw hw;

	unsigned long hw_rate;

	bool restrict_rate_change;



	atomic_t usage_count;
@@ -931,7 +930,7 @@ static int rk_hdptx_tmds_ropll_cmn_config(struct rk_hdptx_phy *hdptx) 
{

	const struct ropll_config *cfg = NULL;

	struct ropll_config rc = {0};

	int ret, i;

	int i;



	if (!hdptx->hdmi_cfg.tmds_char_rate)

		return 0;
@@ -993,12 +992,7 @@ static int rk_hdptx_tmds_ropll_cmn_config(struct rk_hdptx_phy *hdptx) 
	regmap_update_bits(hdptx->regmap, CMN_REG(0086), PLL_PCG_CLK_EN_MASK,

			   FIELD_PREP(PLL_PCG_CLK_EN_MASK, 0x1));



	ret = rk_hdptx_post_enable_pll(hdptx);

	if (!ret)

		hdptx->hw_rate = DIV_ROUND_CLOSEST_ULL(hdptx->hdmi_cfg.tmds_char_rate * 8,

						       hdptx->hdmi_cfg.bpc);



	return ret;

	return rk_hdptx_post_enable_pll(hdptx);

}



static int rk_hdptx_tmds_ropll_mode_config(struct rk_hdptx_phy *hdptx)
@@ -1903,9 +1897,6 @@ static unsigned long rk_hdptx_phy_clk_recalc_rate(struct clk_hw *hw, 
	u64 rate;

	int ret;



	if (hdptx->hw_rate)

		return hdptx->hw_rate;



	ret = regmap_read(hdptx->grf, GRF_HDPTX_CON0, &status);

	if (ret || !(status & HDPTX_I_PLL_EN))

		return 0;