Commit 6719ab82 authored by Kenneth Feng's avatar Kenneth Feng Committed by Alex Deucher
Browse files

drm/amdgpu/pm: add gen5 display to the user on smu v14.0.2/3 



add gen5 display to the user on smu v14.0.2/3

Signed-off-by: default avatarKenneth Feng <kenneth.feng@amd.com>
Reviewed-by: default avatarYang Wang <kevinyang.wang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org # 6.11.x
parent 097c69d4

drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c

+6 −2
Original line number Diff line number Diff line
@@ -1704,7 +1704,9 @@ static int smu_smc_hw_setup(struct smu_context *smu) 
		return ret;

	}



	if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4)

	if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN5)

		pcie_gen = 4;

	else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4)

		pcie_gen = 3;

	else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)

		pcie_gen = 2;
@@ -1717,7 +1719,9 @@ static int smu_smc_hw_setup(struct smu_context *smu) 
	 * Bit 15:8:  PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4

	 * Bit 7:0:   PCIE lane width, 1 to 7 corresponds is x1 to x32

	 */

	if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16)

	if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X32)

		pcie_width = 7;

	else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16)

		pcie_width = 6;

	else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12)

		pcie_width = 5;

drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0.h

+1 −1
Original line number Diff line number Diff line
@@ -53,7 +53,7 @@ 
#define CTF_OFFSET_MEM			5



extern const int decoded_link_speed[5];

extern const int decoded_link_width[7];

extern const int decoded_link_width[8];



#define DECODE_GEN_SPEED(gen_speed_idx)		(decoded_link_speed[gen_speed_idx])

#define DECODE_LANE_WIDTH(lane_width_idx)	(decoded_link_width[lane_width_idx])

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c

+1 −1
Original line number Diff line number Diff line
@@ -49,7 +49,7 @@ 
#define regMP1_SMN_IH_SW_INT_CTRL_mp1_14_0_0_BASE_IDX   0



const int decoded_link_speed[5] = {1, 2, 3, 4, 5};

const int decoded_link_width[7] = {0, 1, 2, 4, 8, 12, 16};

const int decoded_link_width[8] = {0, 1, 2, 4, 8, 12, 16, 32};

/*

 * DO NOT use these for err/warn/info/debug messages.

 * Use dev_err, dev_warn, dev_info and dev_dbg instead.

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c

+4 −2
Original line number Diff line number Diff line
@@ -1173,13 +1173,15 @@ static int smu_v14_0_2_print_clk_levels(struct smu_context *smu, 
					(pcie_table->pcie_gen[i] == 0) ? "2.5GT/s," :

					(pcie_table->pcie_gen[i] == 1) ? "5.0GT/s," :

					(pcie_table->pcie_gen[i] == 2) ? "8.0GT/s," :

					(pcie_table->pcie_gen[i] == 3) ? "16.0GT/s," : "",

					(pcie_table->pcie_gen[i] == 3) ? "16.0GT/s," :

					(pcie_table->pcie_gen[i] == 4) ? "32.0GT/s," : "",

					(pcie_table->pcie_lane[i] == 1) ? "x1" :

					(pcie_table->pcie_lane[i] == 2) ? "x2" :

					(pcie_table->pcie_lane[i] == 3) ? "x4" :

					(pcie_table->pcie_lane[i] == 4) ? "x8" :

					(pcie_table->pcie_lane[i] == 5) ? "x12" :

					(pcie_table->pcie_lane[i] == 6) ? "x16" : "",

					(pcie_table->pcie_lane[i] == 6) ? "x16" :

					(pcie_table->pcie_lane[i] == 7) ? "x32" : "",

					pcie_table->clk_freq[i],

					(gen_speed == DECODE_GEN_SPEED(pcie_table->pcie_gen[i])) &&

					(lane_width == DECODE_LANE_WIDTH(pcie_table->pcie_lane[i])) ?