Commit 672a58fc authored by Manivannan Sadhasivam's avatar Manivannan Sadhasivam Committed by Bjorn Andersson
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arm64: dts: qcom: sm8150: Fix the iommu mask used for PCIe controllers 



The iommu mask should be 0x3f as per Qualcomm internal documentation.
Without the correct mask, the PCIe transactions from the endpoint will
result in SMMU faults. Hence, fix it!

Cc: stable@vger.kernel.org # 5.19
Fixes: a1c86c68 ("arm64: dts: qcom: sm8150: Add PCIe nodes")
Signed-off-by: default avatarManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: default avatarKonrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: default avatarBhupesh Sharma <bhupesh.sharma@linaro.org>
Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230224080045.6577-1-manivannan.sadhasivam@linaro.org
parent fe15c26e

arch/arm64/boot/dts/qcom/sm8150.dtsi

+2 −2
Original line number Diff line number Diff line
@@ -1826,7 +1826,7 @@ pcie0: pci@1c00000 { 
				      "slave_q2a",

				      "tbu";



			iommus = <&apps_smmu 0x1d80 0x7f>;

			iommus = <&apps_smmu 0x1d80 0x3f>;

			iommu-map = <0x0   &apps_smmu 0x1d80 0x1>,

				    <0x100 &apps_smmu 0x1d81 0x1>;
@@ -1925,7 +1925,7 @@ pcie1: pci@1c08000 { 
			assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;

			assigned-clock-rates = <19200000>;



			iommus = <&apps_smmu 0x1e00 0x7f>;

			iommus = <&apps_smmu 0x1e00 0x3f>;

			iommu-map = <0x0   &apps_smmu 0x1e00 0x1>,

				    <0x100 &apps_smmu 0x1e01 0x1>;