Commit 673167d9 authored by Satyanarayana K V P's avatar Satyanarayana K V P Committed by Matthew Brost
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drm/xe: Use PPGTT addresses for TLB invalidation to avoid GGTT fixups 



The migrate VM builds the CCS metadata save/restore batch buffer (BB) in
advance and retains it so the GuC can submit it directly when saving a
VM’s state.

When a VM migrates between VFs, the GGTT base can change. Any GGTT-based
addresses embedded in the BB would then have to be parsed and patched.

Use PPGTT addresses in the BB (including for TLB invalidation) so the BB
remains GGTT-agnostic and requires no address fixups during migration.

Signed-off-by: default avatarSatyanarayana K V P <satyanarayana.k.v.p@intel.com>
Signed-off-by: default avatarMatthew Brost <matthew.brost@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Matthew Brost <matthew.brost@intel.com>
Reviewed-by: default avatarMatthew Brost <matthew.brost@intel.com>
Link: https://lore.kernel.org/r/20251008214532.3442967-31-matthew.brost@intel.com
parent 3b569119

drivers/gpu/drm/xe/xe_migrate.c

+20 −8
Original line number Diff line number Diff line
@@ -980,15 +980,27 @@ struct xe_lrc *xe_migrate_lrc(struct xe_migrate *migrate) 
	return migrate->q->lrc[0];

}



static int emit_flush_invalidate(struct xe_exec_queue *q, u32 *dw, int i,

				 u32 flags)

static u64 migrate_vm_ppgtt_addr_tlb_inval(void)

{

	struct xe_lrc *lrc = xe_exec_queue_lrc(q);

	/*

	 * The migrate VM is self-referential so it can modify its own PTEs (see

	 * pte_update_size() or emit_pte() functions). We reserve NUM_KERNEL_PDE

	 * entries for kernel operations (copies, clears, CCS migrate), and

	 * suballocate the rest to user operations (binds/unbinds). With

	 * NUM_KERNEL_PDE = 15, NUM_KERNEL_PDE - 1 is already used for PTE updates,

	 * so assign NUM_KERNEL_PDE - 2 for TLB invalidation.

	 */

	return (NUM_KERNEL_PDE - 2) * XE_PAGE_SIZE;

}



static int emit_flush_invalidate(u32 *dw, int i, u32 flags)

{

	u64 addr = migrate_vm_ppgtt_addr_tlb_inval();



	dw[i++] = MI_FLUSH_DW | MI_INVALIDATE_TLB | MI_FLUSH_DW_OP_STOREDW |

		  MI_FLUSH_IMM_DW | flags;

	dw[i++] = lower_32_bits(xe_lrc_start_seqno_ggtt_addr(lrc)) |

		  MI_FLUSH_DW_USE_GTT;

	dw[i++] = upper_32_bits(xe_lrc_start_seqno_ggtt_addr(lrc));

	dw[i++] = lower_32_bits(addr);

	dw[i++] = upper_32_bits(addr);

	dw[i++] = MI_NOOP;

	dw[i++] = MI_NOOP;
@@ -1101,11 +1113,11 @@ int xe_migrate_ccs_rw_copy(struct xe_tile *tile, struct xe_exec_queue *q, 


		emit_pte(m, bb, ccs_pt, false, false, &ccs_it, ccs_size, src);



		bb->len = emit_flush_invalidate(q, bb->cs, bb->len, flush_flags);

		bb->len = emit_flush_invalidate(bb->cs, bb->len, flush_flags);

		flush_flags = xe_migrate_ccs_copy(m, bb, src_L0_ofs, src_is_pltt,

						  src_L0_ofs, dst_is_pltt,

						  src_L0, ccs_ofs, true);

		bb->len = emit_flush_invalidate(q, bb->cs, bb->len, flush_flags);

		bb->len = emit_flush_invalidate(bb->cs, bb->len, flush_flags);



		size -= src_L0;

	}