Commit 6733d827 authored by Rob Clark's avatar Rob Clark
Browse files

drm/msm: Update register xml



Sync register xml from mesa commit eb3e0b7164a3 ("freedreno/a6xx: Split
descriptors out into their own file").

Signed-off-by: default avatarRob Clark <robin.clark@oss.qualcomm.com>
Acked-by: default avatarDmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/662470/
parent b74fae54
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+5 −0
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@@ -195,6 +195,11 @@ ADRENO_HEADERS = \
	generated/a4xx.xml.h \
	generated/a5xx.xml.h \
	generated/a6xx.xml.h \
	generated/a6xx_descriptors.xml.h \
	generated/a6xx_enums.xml.h \
	generated/a6xx_perfcntrs.xml.h \
	generated/a7xx_enums.xml.h \
	generated/a7xx_perfcntrs.xml.h \
	generated/a6xx_gmu.xml.h \
	generated/adreno_common.xml.h \
	generated/adreno_pm4.xml.h \
+1 −1
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@@ -1335,7 +1335,7 @@ static const uint32_t a7xx_pwrup_reglist_regs[] = {
	REG_A6XX_RB_NC_MODE_CNTL,
	REG_A6XX_RB_CMP_DBG_ECO_CNTL,
	REG_A7XX_GRAS_NC_MODE_CNTL,
	REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE,
	REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE_ENABLE,
	REG_A6XX_UCHE_GBIF_GX_CONFIG,
	REG_A6XX_UCHE_CLIENT_PF,
	REG_A6XX_TPL1_DBG_ECO_CNTL1,
+4 −0
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@@ -6,6 +6,10 @@


#include "adreno_gpu.h"
#include "a6xx_enums.xml.h"
#include "a7xx_enums.xml.h"
#include "a6xx_perfcntrs.xml.h"
#include "a7xx_perfcntrs.xml.h"
#include "a6xx.xml.h"

#include "a6xx_gmu.h"
+1 −1
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@@ -158,7 +158,7 @@ static int a6xx_crashdumper_run(struct msm_gpu *gpu,
	/* Make sure all pending memory writes are posted */
	wmb();

	gpu_write64(gpu, REG_A6XX_CP_CRASH_SCRIPT_BASE, dumper->iova);
	gpu_write64(gpu, REG_A6XX_CP_CRASH_DUMP_SCRIPT_BASE, dumper->iova);

	gpu_write(gpu, REG_A6XX_CP_CRASH_DUMP_CNTL, 1);

+1 −1
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@@ -212,7 +212,7 @@ static const struct a6xx_shader_block {
	SHADER(A6XX_SP_LB_5_DATA, 0x200),
	SHADER(A6XX_SP_CB_BINDLESS_DATA, 0x800),
	SHADER(A6XX_SP_CB_LEGACY_DATA, 0x280),
	SHADER(A6XX_SP_UAV_DATA, 0x80),
	SHADER(A6XX_SP_GFX_UAV_BASE_DATA, 0x80),
	SHADER(A6XX_SP_INST_TAG, 0x80),
	SHADER(A6XX_SP_CB_BINDLESS_TAG, 0x80),
	SHADER(A6XX_SP_TMO_UMO_TAG, 0x80),
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