Commit 67475eb9 authored by Jakub Kicinski's avatar Jakub Kicinski
Browse files

Merge branch 'mt7530-dsa-subdriver-improvements-act-i' 

Arınç ÜNAL says:

====================
MT7530 DSA Subdriver Improvements Act I

This patch series simplifies the MT7530 DSA subdriver and improves the
logic of the support for MT7530, MT7531, and the switch on the MT7988 SoC.

I have done a simple ping test to confirm basic communication on all switch
ports on MCM and standalone MT7530, and MT7531 switch with this patch
series applied.

MT7621 Unielec, MCM MT7530:

rgmii-only-gmac0-mt7621-unielec-u7621-06-16m.dtb
gmac0-and-gmac1-mt7621-unielec-u7621-06-16m.dtb

tftpboot 0x80008000 mips-uzImage.bin; tftpboot 0x83000000 mips-rootfs.cpio.uboot; tftpboot 0x83f00000 $dtb; bootm 0x80008000 0x83000000 0x83f00000

MT7622 Bananapi, MT7531:

gmac0-and-gmac1-mt7622-bananapi-bpi-r64.dtb

tftpboot 0x40000000 arm64-Image; tftpboot 0x45000000 arm64-rootfs.cpio.uboot; tftpboot 0x4a000000 $dtb; booti 0x40000000 0x45000000 0x4a000000

MT7623 Bananapi, standalone MT7530:

rgmii-only-gmac0-mt7623n-bananapi-bpi-r2.dtb
gmac0-and-gmac1-mt7623n-bananapi-bpi-r2.dtb

tftpboot 0x80008000 arm-zImage; tftpboot 0x83000000 arm-rootfs.cpio.uboot; tftpboot 0x83f00000 $dtb; bootz 0x80008000 0x83000000 0x83f00000

This patch series is the continuation of the patch series linked below.

https://lore.kernel.org/r/20230522121532.86610-1-arinc.unal@arinc9.com

v2: https://lore.kernel.org/r/20231227044347.107291-1-arinc.unal@arinc9.com
v1: https://lore.kernel.org/r/20231118123205.266819-1-arinc.unal@arinc9.com



Signed-off-by: default avatarArınç ÜNAL <arinc.unal@arinc9.com>
====================

Link: https://lore.kernel.org/r/20240122-for-netnext-mt7530-improvements-1-v3-0-042401f2b279@arinc9.com


Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parents 723de3eb 04a22bef

drivers/net/dsa/mt7530-mdio.c

+2 −5
Original line number Diff line number Diff line
@@ -81,17 +81,14 @@ static const struct regmap_bus mt7530_regmap_bus = { 
};



static int

mt7531_create_sgmii(struct mt7530_priv *priv, bool dual_sgmii)

mt7531_create_sgmii(struct mt7530_priv *priv)

{

	struct regmap_config *mt7531_pcs_config[2] = {};

	struct phylink_pcs *pcs;

	struct regmap *regmap;

	int i, ret = 0;



	/* MT7531AE has two SGMII units for port 5 and port 6

	 * MT7531BE has only one SGMII unit for port 6

	 */

	for (i = dual_sgmii ? 0 : 1; i < 2; i++) {

	for (i = priv->p5_sgmii ? 0 : 1; i < 2; i++) {

		mt7531_pcs_config[i] = devm_kzalloc(priv->dev,

						    sizeof(struct regmap_config),

						    GFP_KERNEL);

drivers/net/dsa/mt7530.c

+75 −60
Original line number Diff line number Diff line
@@ -487,15 +487,6 @@ mt7530_pad_clk_setup(struct dsa_switch *ds, phy_interface_t interface) 
	return 0;

}



static bool mt7531_dual_sgmii_supported(struct mt7530_priv *priv)

{

	u32 val;



	val = mt7530_read(priv, MT7531_TOP_SIG_SR);



	return (val & PAD_DUAL_SGMII_EN) != 0;

}



static int

mt7531_pad_setup(struct dsa_switch *ds, phy_interface_t interface)

{
@@ -510,9 +501,6 @@ mt7531_pll_setup(struct mt7530_priv *priv) 
	u32 xtal;

	u32 val;



	if (mt7531_dual_sgmii_supported(priv))

		return;



	val = mt7530_read(priv, MT7531_CREV);

	top_sig = mt7530_read(priv, MT7531_TOP_SIG_SR);

	hwstrap = mt7530_read(priv, MT7531_HWTRAP);
@@ -920,8 +908,6 @@ static const char *p5_intf_modes(unsigned int p5_interface) 
		return "PHY P4";

	case P5_INTF_SEL_GMAC5:

		return "GMAC5";

	case P5_INTF_SEL_GMAC5_SGMII:

		return "GMAC5_SGMII";

	default:

		return "unknown";

	}
@@ -956,9 +942,6 @@ static void mt7530_setup_port5(struct dsa_switch *ds, phy_interface_t interface) 
		/* MT7530_P5_MODE_GMAC: P5 -> External phy or 2nd GMAC */

		val &= ~MHWTRAP_P5_DIS;

		break;

	case P5_DISABLED:

		interface = PHY_INTERFACE_MODE_NA;

		break;

	default:

		dev_err(ds->dev, "Unsupported p5_intf_sel %d\n",

			priv->p5_intf_sel);
@@ -992,8 +975,6 @@ static void mt7530_setup_port5(struct dsa_switch *ds, phy_interface_t interface) 
	dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, intf_sel=%s, phy-mode=%s\n",

		val, p5_intf_modes(priv->p5_intf_sel), phy_modes(interface));



	priv->p5_interface = interface;



unlock_exit:

	mutex_unlock(&priv->reg_mutex);

}
@@ -1035,10 +1016,6 @@ mt753x_cpu_port_enable(struct dsa_switch *ds, int port) 
	mt7530_set(priv, MT7530_MFC, BC_FFP(BIT(port)) | UNM_FFP(BIT(port)) |

		   UNU_FFP(BIT(port)));



	/* Set CPU port number */

	if (priv->id == ID_MT7530 || priv->id == ID_MT7621)

		mt7530_rmw(priv, MT7530_MFC, CPU_MASK, CPU_EN | CPU_PORT(port));



	/* Add the CPU port to the CPU port bitmap for MT7531 and the switch on

	 * the MT7988 SoC. Trapped frames will be forwarded to the CPU port that

	 * is affine to the inbound user port.
@@ -2344,16 +2321,13 @@ mt7530_setup(struct dsa_switch *ds) 
		return ret;



	/* Setup port 5 */

	priv->p5_intf_sel = P5_DISABLED;

	interface = PHY_INTERFACE_MODE_NA;



	if (!dsa_is_unused_port(ds, 5)) {

		priv->p5_intf_sel = P5_INTF_SEL_GMAC5;

		ret = of_get_phy_mode(dsa_to_port(ds, 5)->dn, &interface);

		if (ret && ret != -ENODEV)

			return ret;

	} else {

		/* Scan the ethernet nodes. look for GMAC1, lookup used phy */

		/* Scan the ethernet nodes. Look for GMAC1, lookup the used PHY.

		 * Set priv->p5_intf_sel to the appropriate value if PHY muxing

		 * is detected.

		 */

		for_each_child_of_node(dn, mac_np) {

			if (!of_device_is_compatible(mac_np,

						     "mediatek,eth-mac"))
@@ -2384,6 +2358,10 @@ mt7530_setup(struct dsa_switch *ds) 
			of_node_put(phy_node);

			break;

		}



		if (priv->p5_intf_sel == P5_INTF_SEL_PHY_P0 ||

		    priv->p5_intf_sel == P5_INTF_SEL_PHY_P4)

			mt7530_setup_port5(ds, interface);

	}



#ifdef CONFIG_GPIOLIB
@@ -2394,8 +2372,6 @@ mt7530_setup(struct dsa_switch *ds) 
	}

#endif /* CONFIG_GPIOLIB */



	mt7530_setup_port5(ds, interface);



	/* Flush the FDB table */

	ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL);

	if (ret < 0)
@@ -2492,6 +2468,12 @@ mt7531_setup(struct dsa_switch *ds) 
		return -ENODEV;

	}



	/* MT7531AE has got two SGMII units. One for port 5, one for port 6.

	 * MT7531BE has got only one SGMII unit which is for port 6.

	 */

	val = mt7530_read(priv, MT7531_TOP_SIG_SR);

	priv->p5_sgmii = !!(val & PAD_DUAL_SGMII_EN);



	/* all MACs must be forced link-down before sw reset */

	for (i = 0; i < MT7530_NUM_PORTS; i++)

		mt7530_write(priv, MT7530_PMCR_P(i), MT7531_FORCE_LNK);
@@ -2501,21 +2483,18 @@ mt7531_setup(struct dsa_switch *ds) 
		     SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST |

		     SYS_CTRL_REG_RST);



	if (!priv->p5_sgmii) {

		mt7531_pll_setup(priv);



	if (mt7531_dual_sgmii_supported(priv)) {

		priv->p5_intf_sel = P5_INTF_SEL_GMAC5_SGMII;



	} else {

		/* Let ds->user_mii_bus be able to access external phy. */

		mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO11_RG_RXD2_MASK,

			   MT7531_EXT_P_MDC_11);

		mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO12_RG_RXD3_MASK,

			   MT7531_EXT_P_MDIO_12);

	} else {

		priv->p5_intf_sel = P5_INTF_SEL_GMAC5;

	}

	dev_dbg(ds->dev, "P5 support %s interface\n",

		p5_intf_modes(priv->p5_intf_sel));



	if (!dsa_is_unused_port(ds, 5))

		priv->p5_intf_sel = P5_INTF_SEL_GMAC5;



	mt7530_rmw(priv, MT7531_GPIO_MODE0, MT7531_GPIO0_MASK,

		   MT7531_GPIO0_INTERRUPT);
@@ -2553,12 +2532,14 @@ static void mt7530_mac_port_get_caps(struct dsa_switch *ds, int port, 
				     struct phylink_config *config)

{

	switch (port) {

	case 0 ... 4: /* Internal phy */

	/* Ports which are connected to switch PHYs. There is no MII pinout. */

	case 0 ... 4:

		__set_bit(PHY_INTERFACE_MODE_GMII,

			  config->supported_interfaces);

		break;



	case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */

	/* Port 5 supports rgmii with delays, mii, and gmii. */

	case 5:

		phy_interface_set_rgmii(config->supported_interfaces);

		__set_bit(PHY_INTERFACE_MODE_MII,

			  config->supported_interfaces);
@@ -2566,7 +2547,8 @@ static void mt7530_mac_port_get_caps(struct dsa_switch *ds, int port, 
			  config->supported_interfaces);

		break;



	case 6: /* 1st cpu port */

	/* Port 6 supports rgmii and trgmii. */

	case 6:

		__set_bit(PHY_INTERFACE_MODE_RGMII,

			  config->supported_interfaces);

		__set_bit(PHY_INTERFACE_MODE_TRGMII,
@@ -2575,30 +2557,30 @@ static void mt7530_mac_port_get_caps(struct dsa_switch *ds, int port, 
	}

}



static bool mt7531_is_rgmii_port(struct mt7530_priv *priv, u32 port)

{

	return (port == 5) && (priv->p5_intf_sel != P5_INTF_SEL_GMAC5_SGMII);

}



static void mt7531_mac_port_get_caps(struct dsa_switch *ds, int port,

				     struct phylink_config *config)

{

	struct mt7530_priv *priv = ds->priv;



	switch (port) {

	case 0 ... 4: /* Internal phy */

	/* Ports which are connected to switch PHYs. There is no MII pinout. */

	case 0 ... 4:

		__set_bit(PHY_INTERFACE_MODE_GMII,

			  config->supported_interfaces);

		break;



	case 5: /* 2nd cpu port supports either rgmii or sgmii/8023z */

		if (mt7531_is_rgmii_port(priv, port)) {

	/* Port 5 supports rgmii with delays on MT7531BE, sgmii/802.3z on

	 * MT7531AE.

	 */

	case 5:

		if (!priv->p5_sgmii) {

			phy_interface_set_rgmii(config->supported_interfaces);

			break;

		}

		fallthrough;



	case 6: /* 1st cpu port supports sgmii/8023z only */

	/* Port 6 supports sgmii/802.3z. */

	case 6:

		__set_bit(PHY_INTERFACE_MODE_SGMII,

			  config->supported_interfaces);

		__set_bit(PHY_INTERFACE_MODE_1000BASEX,
@@ -2617,11 +2599,13 @@ static void mt7988_mac_port_get_caps(struct dsa_switch *ds, int port, 
	phy_interface_zero(config->supported_interfaces);



	switch (port) {

	case 0 ... 4: /* Internal phy */

	/* Ports which are connected to switch PHYs. There is no MII pinout. */

	case 0 ... 4:

		__set_bit(PHY_INTERFACE_MODE_INTERNAL,

			  config->supported_interfaces);

		break;



	/* Port 6 is connected to SoC's XGMII MAC. There is no MII pinout. */

	case 6:

		__set_bit(PHY_INTERFACE_MODE_INTERNAL,

			  config->supported_interfaces);
@@ -2659,7 +2643,7 @@ static int mt7531_rgmii_setup(struct mt7530_priv *priv, u32 port, 
{

	u32 val;



	if (!mt7531_is_rgmii_port(priv, port)) {

	if (priv->p5_sgmii) {

		dev_err(priv->dev, "RGMII mode is not available for port %d\n",

			port);

		return -EINVAL;
@@ -2785,12 +2769,12 @@ mt753x_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 
	u32 mcr_cur, mcr_new;



	switch (port) {

	case 0 ... 4: /* Internal phy */

	case 0 ... 4:

		if (state->interface != PHY_INTERFACE_MODE_GMII &&

		    state->interface != PHY_INTERFACE_MODE_INTERNAL)

			goto unsupported;

		break;

	case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */

	case 5:

		if (priv->p5_interface == state->interface)

			break;
@@ -2800,7 +2784,7 @@ mt753x_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 
		if (priv->p5_intf_sel != P5_DISABLED)

			priv->p5_interface = state->interface;

		break;

	case 6: /* 1st cpu port */

	case 6:

		if (priv->p6_interface == state->interface)

			break;
@@ -2903,7 +2887,7 @@ mt7531_cpu_port_config(struct dsa_switch *ds, int port) 


	switch (port) {

	case 5:

		if (mt7531_is_rgmii_port(priv, port))

		if (!priv->p5_sgmii)

			interface = PHY_INTERFACE_MODE_RGMII;

		else

			interface = PHY_INTERFACE_MODE_2500BASEX;
@@ -3055,7 +3039,7 @@ mt753x_setup(struct dsa_switch *ds) 
		mt7530_free_irq_common(priv);



	if (priv->create_sgmii) {

		ret = priv->create_sgmii(priv, mt7531_dual_sgmii_supported(priv));

		ret = priv->create_sgmii(priv);

		if (ret && priv->irq)

			mt7530_free_irq(priv);

	}
@@ -3093,6 +3077,36 @@ static int mt753x_set_mac_eee(struct dsa_switch *ds, int port, 
	return 0;

}



static void

mt753x_conduit_state_change(struct dsa_switch *ds,

			    const struct net_device *conduit,

			    bool operational)

{

	struct dsa_port *cpu_dp = conduit->dsa_ptr;

	struct mt7530_priv *priv = ds->priv;

	int val = 0;

	u8 mask;



	/* Set the CPU port to trap frames to for MT7530. Trapped frames will be

	 * forwarded to the numerically smallest CPU port whose conduit

	 * interface is up.

	 */

	if (priv->id != ID_MT7530 && priv->id != ID_MT7621)

		return;



	mask = BIT(cpu_dp->index);



	if (operational)

		priv->active_cpu_ports |= mask;

	else

		priv->active_cpu_ports &= ~mask;



	if (priv->active_cpu_ports)

		val = CPU_EN | CPU_PORT(__ffs(priv->active_cpu_ports));



	mt7530_rmw(priv, MT7530_MFC, CPU_EN | CPU_PORT_MASK, val);

}



static int mt7988_pad_setup(struct dsa_switch *ds, phy_interface_t interface)

{

	return 0;
@@ -3148,6 +3162,7 @@ const struct dsa_switch_ops mt7530_switch_ops = { 
	.phylink_mac_link_up	= mt753x_phylink_mac_link_up,

	.get_mac_eee		= mt753x_get_mac_eee,

	.set_mac_eee		= mt753x_set_mac_eee,

	.conduit_state_change	= mt753x_conduit_state_change,

};

EXPORT_SYMBOL_GPL(mt7530_switch_ops);

drivers/net/dsa/mt7530.h

+10 −6
Original line number Diff line number Diff line
@@ -41,8 +41,8 @@ enum mt753x_id { 
#define  UNU_FFP(x)			(((x) & 0xff) << 8)

#define  UNU_FFP_MASK			UNU_FFP(~0)

#define  CPU_EN				BIT(7)

#define  CPU_PORT(x)			((x) << 4)

#define  CPU_MASK			(0xf << 4)

#define  CPU_PORT_MASK			GENMASK(6, 4)

#define  CPU_PORT(x)			FIELD_PREP(CPU_PORT_MASK, x)

#define  MIRROR_EN			BIT(3)

#define  MIRROR_PORT(x)			((x) & 0x7)

#define  MIRROR_MASK			0x7
@@ -683,11 +683,10 @@ struct mt7530_port { 


/* Port 5 interface select definitions */

enum p5_interface_select {

	P5_DISABLED = 0,

	P5_DISABLED,

	P5_INTF_SEL_PHY_P0,

	P5_INTF_SEL_PHY_P4,

	P5_INTF_SEL_GMAC5,

	P5_INTF_SEL_GMAC5_SGMII,

};



struct mt7530_priv;
@@ -756,10 +755,13 @@ struct mt753x_info { 
 *			registers

 * @p6_interface	Holding the current port 6 interface

 * @p5_intf_sel:	Holding the current port 5 interface select

 * @p5_sgmii:		Flag for distinguishing if port 5 of the MT7531 switch

 *			has got SGMII

 * @irq:		IRQ number of the switch

 * @irq_domain:		IRQ domain of the switch irq_chip

 * @irq_enable:		IRQ enable bits, synced to SYS_INT_EN

 * @create_sgmii:	Pointer to function creating SGMII PCS instance(s)

 * @active_cpu_ports:	Holding the active CPU ports

 */

struct mt7530_priv {

	struct device		*dev;
@@ -775,7 +777,8 @@ struct mt7530_priv { 
	bool			mcm;

	phy_interface_t		p6_interface;

	phy_interface_t		p5_interface;

	unsigned int		p5_intf_sel;

	enum p5_interface_select p5_intf_sel;

	bool			p5_sgmii;

	u8			mirror_rx;

	u8			mirror_tx;

	struct mt7530_port	ports[MT7530_NUM_PORTS];
@@ -785,7 +788,8 @@ struct mt7530_priv { 
	int irq;

	struct irq_domain *irq_domain;

	u32 irq_enable;

	int (*create_sgmii)(struct mt7530_priv *priv, bool dual_sgmii);

	int (*create_sgmii)(struct mt7530_priv *priv);

	u8 active_cpu_ports;

};



struct mt7530_hw_vlan_entry {