Commit 67934f24 authored by Marek Vasut's avatar Marek Vasut Committed by Liviu Dudau
Browse files

arm64: dts: imx95: Describe Mali G310 GPU 



The instance of the GPU populated in i.MX95 is the G310, describe this
GPU in the DT. Include dummy GPU voltage regulator and OPP tables.

Reviewed-by: default avatarFrank Li <Frank.Li@nxp.com>
Signed-off-by: default avatarMarek Vasut <marek.vasut@mailbox.org>
Link: https://patch.msgid.link/20251102160927.45157-2-marek.vasut@mailbox.org


Signed-off-by: default avatarLiviu Dudau <liviu.dudau@arm.com>
parent 6918b7e8

arch/arm64/boot/dts/freescale/imx95.dtsi

+37 −0
Original line number Diff line number Diff line
@@ -250,6 +250,28 @@ dummy: clock-dummy { 
		clock-output-names = "dummy";

	};



	gpu_opp_table: opp-table {

		compatible = "operating-points-v2";



		opp-500000000 {

			opp-hz = /bits/ 64 <500000000>;

			opp-hz-real = /bits/ 64 <500000000>;

			opp-microvolt = <920000>;

		};



		opp-800000000 {

			opp-hz = /bits/ 64 <800000000>;

			opp-hz-real = /bits/ 64 <800000000>;

			opp-microvolt = <920000>;

		};



		opp-1000000000 {

			opp-hz = /bits/ 64 <1000000000>;

			opp-hz-real = /bits/ 64 <1000000000>;

			opp-microvolt = <920000>;

		};

	};



	clk_ext1: clock-ext1 {

		compatible = "fixed-clock";

		#clock-cells = <0>;
@@ -2138,6 +2160,21 @@ netc_emdio: mdio@0,0 { 
			};

		};



		gpu: gpu@4d900000 {

			compatible = "nxp,imx95-mali", "arm,mali-valhall-csf";

			reg = <0 0x4d900000 0 0x480000>;

			clocks = <&scmi_clk IMX95_CLK_GPU>, <&scmi_clk IMX95_CLK_GPUAPB>;

			clock-names = "core", "coregroup";

			interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "job", "mmu", "gpu";

			operating-points-v2 = <&gpu_opp_table>;

			power-domains = <&scmi_devpd IMX95_PD_GPU>;

			#cooling-cells = <2>;

			dynamic-power-coefficient = <1013>;

		};



		ddr-pmu@4e090dc0 {

			compatible = "fsl,imx95-ddr-pmu", "fsl,imx93-ddr-pmu";

			reg = <0x0 0x4e090dc0 0x0 0x200>;