Commit 67c01705 authored by Kamil Horák - 2N's avatar Kamil Horák - 2N Committed by Jakub Kicinski
Browse files

net: phy: MII-Lite PHY interface mode 



Some Broadcom PHYs are capable to operate in simplified MII mode,
without TXER, RXER, CRS and COL signals as defined for the MII.
The MII-Lite mode can be used on most Ethernet controllers with full
MII interface by just leaving the input signals (RXER, CRS, COL)
inactive. The absence of COL signal makes half-duplex link modes
impossible but does not interfere with BroadR-Reach link modes on
Broadcom PHYs, because they are all full-duplex only.

Add MII-Lite interface mode, especially for Broadcom two-wire PHYs.

Signed-off-by: default avatarKamil Horák - 2N <kamilh@axis.com>
Reviewed-by: default avatarMaxime Chevallier <maxime.chevallier@bootlin.com>
Reviewed-by: default avatarFlorian Fainelli <florian.fainelli@broadcom.com>
Reviewed-by: default avatarRussell King (Oracle) <rmk+kernel@armlinux.org.uk>
Link: https://patch.msgid.link/20250708090140.61355-2-kamilh@axis.com


Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parent 6dfcbd7d

Documentation/networking/phy.rst

+7 −0
Original line number Diff line number Diff line
@@ -333,6 +333,13 @@ Some of the interface modes are described below: 
    SerDes lane, each port having speeds of 2.5G / 1G / 100M / 10M achieved

    through symbol replication. The PCS expects the standard USXGMII code word.



``PHY_INTERFACE_MODE_MIILITE``

    Non-standard, simplified MII mode, without TXER, RXER, CRS and COL signals

    as defined for the MII. The absence of COL signal makes half-duplex link

    modes impossible but does not interfere with BroadR-Reach link modes on

    Broadcom (and other two-wire Ethernet) PHYs, because they are full-duplex

    only.



Pause frames / flow control

===========================

drivers/net/phy/phy-core.c

+1 −0
Original line number Diff line number Diff line
@@ -115,6 +115,7 @@ int phy_interface_num_ports(phy_interface_t interface) 
		return 0;

	case PHY_INTERFACE_MODE_INTERNAL:

	case PHY_INTERFACE_MODE_MII:

	case PHY_INTERFACE_MODE_MIILITE:

	case PHY_INTERFACE_MODE_GMII:

	case PHY_INTERFACE_MODE_TBI:

	case PHY_INTERFACE_MODE_REVMII:

drivers/net/phy/phy_caps.c

+4 −0
Original line number Diff line number Diff line
@@ -316,6 +316,10 @@ unsigned long phy_caps_from_interface(phy_interface_t interface) 
		link_caps |= BIT(LINK_CAPA_100HD) | BIT(LINK_CAPA_100FD);

		break;



	case PHY_INTERFACE_MODE_MIILITE:

		link_caps |= BIT(LINK_CAPA_10FD) | BIT(LINK_CAPA_100FD);

		break;



	case PHY_INTERFACE_MODE_TBI:

	case PHY_INTERFACE_MODE_MOCA:

	case PHY_INTERFACE_MODE_RTBI:

drivers/net/phy/phylink.c

+1 −0
Original line number Diff line number Diff line
@@ -237,6 +237,7 @@ static int phylink_interface_max_speed(phy_interface_t interface) 
	case PHY_INTERFACE_MODE_SMII:

	case PHY_INTERFACE_MODE_REVMII:

	case PHY_INTERFACE_MODE_MII:

	case PHY_INTERFACE_MODE_MIILITE:

		return SPEED_100;



	case PHY_INTERFACE_MODE_TBI:

include/linux/phy.h

+4 −0
Original line number Diff line number Diff line
@@ -106,6 +106,7 @@ extern const int phy_basic_ports_array[3]; 
 * @PHY_INTERFACE_MODE_50GBASER: 50GBase-R - with Clause 134 FEC

 * @PHY_INTERFACE_MODE_LAUI: 50 Gigabit Attachment Unit Interface

 * @PHY_INTERFACE_MODE_100GBASEP: 100GBase-P - with Clause 134 FEC

 * @PHY_INTERFACE_MODE_MIILITE: MII-Lite - MII without RXER TXER CRS COL

 * @PHY_INTERFACE_MODE_MAX: Book keeping

 *

 * Describes the interface between the MAC and PHY.
@@ -150,6 +151,7 @@ typedef enum { 
	PHY_INTERFACE_MODE_50GBASER,

	PHY_INTERFACE_MODE_LAUI,

	PHY_INTERFACE_MODE_100GBASEP,

	PHY_INTERFACE_MODE_MIILITE,

	PHY_INTERFACE_MODE_MAX,

} phy_interface_t;
@@ -272,6 +274,8 @@ static inline const char *phy_modes(phy_interface_t interface) 
		return "laui";

	case PHY_INTERFACE_MODE_100GBASEP:

		return "100gbase-p";

	case PHY_INTERFACE_MODE_MIILITE:

		return "mii-lite";

	default:

		return "unknown";

	}