Commit 68047c48 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'char-misc-6.3-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc 

Pull char/misc driver fixes from Greg KH:
 "Here are a small set of various small driver changes for 6.3-rc6.
  Included in here are:

   - iio driver fixes for reported problems

   - coresight hwtracing bugfix for reported problem

   - small counter driver bugfixes

  All have been in linux-next for a while with no reported problems"

* tag 'char-misc-6.3-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc:
  coresight: etm4x: Do not access TRCIDR1 for identification
  coresight-etm4: Fix for() loop drvdata->nr_addr_cmp range bug
  iio: adc: ti-ads7950: Set `can_sleep` flag for GPIO chip
  iio: adc: palmas_gpadc: fix NULL dereference on rmmod
  counter: 104-quad-8: Fix Synapse action reported for Index signals
  counter: 104-quad-8: Fix race condition between FLAG and CNTR reads
  iio: adc: max11410: fix read_poll_timeout() usage
  iio: dac: cio-dac: Fix max DAC write value check for 12-bit
  iio: light: cm32181: Unregister second I2C client if present
  iio: accel: kionix-kx022a: Get the timestamp from the driver's private data in the trigger_handler
  iio: adc: ad7791: fix IRQ flags
  iio: buffer: make sure O_NONBLOCK is respected
  iio: buffer: correctly return bytes written in output buffers
  iio: light: vcnl4000: Fix WARN_ON on uninitialized lock
  iio: adis16480: select CONFIG_CRC32
  drivers: iio: adc: ltc2497: fix LSB shift
  iio: adc: qcom-spmi-adc5: Fix the channel name
parents aa46fe36 4bffd2c7

drivers/counter/104-quad-8.c

+9 −22
Original line number Diff line number Diff line
@@ -97,10 +97,6 @@ struct quad8 { 
	struct quad8_reg __iomem *reg;

};



/* Borrow Toggle flip-flop */

#define QUAD8_FLAG_BT BIT(0)

/* Carry Toggle flip-flop */

#define QUAD8_FLAG_CT BIT(1)

/* Error flag */

#define QUAD8_FLAG_E BIT(4)

/* Up/Down flag */
@@ -133,6 +129,9 @@ struct quad8 { 
#define QUAD8_CMR_QUADRATURE_X2 0x10

#define QUAD8_CMR_QUADRATURE_X4 0x18



/* Each Counter is 24 bits wide */

#define LS7267_CNTR_MAX GENMASK(23, 0)



static int quad8_signal_read(struct counter_device *counter,

			     struct counter_signal *signal,

			     enum counter_signal_level *level)
@@ -156,18 +155,10 @@ static int quad8_count_read(struct counter_device *counter, 
{

	struct quad8 *const priv = counter_priv(counter);

	struct channel_reg __iomem *const chan = priv->reg->channel + count->id;

	unsigned int flags;

	unsigned int borrow;

	unsigned int carry;

	unsigned long irqflags;

	int i;



	flags = ioread8(&chan->control);

	borrow = flags & QUAD8_FLAG_BT;

	carry = !!(flags & QUAD8_FLAG_CT);



	/* Borrow XOR Carry effectively doubles count range */

	*val = (unsigned long)(borrow ^ carry) << 24;

	*val = 0;



	spin_lock_irqsave(&priv->lock, irqflags);
@@ -191,8 +182,7 @@ static int quad8_count_write(struct counter_device *counter, 
	unsigned long irqflags;

	int i;



	/* Only 24-bit values are supported */

	if (val > 0xFFFFFF)

	if (val > LS7267_CNTR_MAX)

		return -ERANGE;



	spin_lock_irqsave(&priv->lock, irqflags);
@@ -378,7 +368,7 @@ static int quad8_action_read(struct counter_device *counter, 


	/* Handle Index signals */

	if (synapse->signal->id >= 16) {

		if (priv->preset_enable[count->id])

		if (!priv->preset_enable[count->id])

			*action = COUNTER_SYNAPSE_ACTION_RISING_EDGE;

		else

			*action = COUNTER_SYNAPSE_ACTION_NONE;
@@ -806,8 +796,7 @@ static int quad8_count_preset_write(struct counter_device *counter, 
	struct quad8 *const priv = counter_priv(counter);

	unsigned long irqflags;



	/* Only 24-bit values are supported */

	if (preset > 0xFFFFFF)

	if (preset > LS7267_CNTR_MAX)

		return -ERANGE;



	spin_lock_irqsave(&priv->lock, irqflags);
@@ -834,8 +823,7 @@ static int quad8_count_ceiling_read(struct counter_device *counter, 
		*ceiling = priv->preset[count->id];

		break;

	default:

		/* By default 0x1FFFFFF (25 bits unsigned) is maximum count */

		*ceiling = 0x1FFFFFF;

		*ceiling = LS7267_CNTR_MAX;

		break;

	}
@@ -850,8 +838,7 @@ static int quad8_count_ceiling_write(struct counter_device *counter, 
	struct quad8 *const priv = counter_priv(counter);

	unsigned long irqflags;



	/* Only 24-bit values are supported */

	if (ceiling > 0xFFFFFF)

	if (ceiling > LS7267_CNTR_MAX)

		return -ERANGE;



	spin_lock_irqsave(&priv->lock, irqflags);

drivers/hwtracing/coresight/coresight-etm4x-core.c

+10 −14
Original line number Diff line number Diff line
@@ -472,7 +472,7 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata) 
		if (etm4x_sspcicrn_present(drvdata, i))

			etm4x_relaxed_write32(csa, config->ss_pe_cmp[i], TRCSSPCICRn(i));

	}

	for (i = 0; i < drvdata->nr_addr_cmp; i++) {

	for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) {

		etm4x_relaxed_write64(csa, config->addr_val[i], TRCACVRn(i));

		etm4x_relaxed_write64(csa, config->addr_acc[i], TRCACATRn(i));

	}
@@ -1070,25 +1070,21 @@ static bool etm4_init_iomem_access(struct etmv4_drvdata *drvdata, 
				   struct csdev_access *csa)

{

	u32 devarch = readl_relaxed(drvdata->base + TRCDEVARCH);

	u32 idr1 = readl_relaxed(drvdata->base + TRCIDR1);



	/*

	 * All ETMs must implement TRCDEVARCH to indicate that

	 * the component is an ETMv4. To support any broken

	 * implementations we fall back to TRCIDR1 check, which

	 * is not really reliable.

	 * the component is an ETMv4. Even though TRCIDR1 also

	 * contains the information, it is part of the "Trace"

	 * register and must be accessed with the OSLK cleared,

	 * with MMIO. But we cannot touch the OSLK until we are

	 * sure this is an ETM. So rely only on the TRCDEVARCH.

	 */

	if ((devarch & ETM_DEVARCH_ID_MASK) == ETM_DEVARCH_ETMv4x_ARCH) {

		drvdata->arch = etm_devarch_to_arch(devarch);

	} else {

		pr_warn("CPU%d: ETM4x incompatible TRCDEVARCH: %x, falling back to TRCIDR1\n",

			smp_processor_id(), devarch);



		if (ETM_TRCIDR1_ARCH_MAJOR(idr1) != ETM_TRCIDR1_ARCH_ETMv4)

	if ((devarch & ETM_DEVARCH_ID_MASK) != ETM_DEVARCH_ETMv4x_ARCH) {

		pr_warn_once("TRCDEVARCH doesn't match ETMv4 architecture\n");

		return false;

		drvdata->arch = etm_trcidr_to_arch(idr1);

	}



	drvdata->arch = etm_devarch_to_arch(devarch);

	*csa = CSDEV_ACCESS_IOMEM(drvdata->base);

	return true;

}

drivers/hwtracing/coresight/coresight-etm4x.h

+6 −14
Original line number Diff line number Diff line
@@ -753,14 +753,12 @@ 
 * TRCDEVARCH	- CoreSight architected register

 *                - Bits[15:12] - Major version

 *                - Bits[19:16] - Minor version

 * TRCIDR1	- ETM architected register

 *                - Bits[11:8] - Major version

 *                - Bits[7:4]  - Minor version

 * We must rely on TRCDEVARCH for the version information,

 * however we don't want to break the support for potential

 * old implementations which might not implement it. Thus

 * we fall back to TRCIDR1 if TRCDEVARCH is not implemented

 * for memory mapped components.

 *

 * We must rely only on TRCDEVARCH for the version information. Even though,

 * TRCIDR1 also provides the architecture version, it is a "Trace" register

 * and as such must be accessed only with Trace power domain ON. This may

 * not be available at probe time.

 *

 * Now to make certain decisions easier based on the version

 * we use an internal representation of the version in the

 * driver, as follows :
@@ -786,12 +784,6 @@ static inline u8 etm_devarch_to_arch(u32 devarch) 
				ETM_DEVARCH_REVISION(devarch));

}



static inline u8 etm_trcidr_to_arch(u32 trcidr1)

{

	return ETM_ARCH_VERSION(ETM_TRCIDR1_ARCH_MAJOR(trcidr1),

				ETM_TRCIDR1_ARCH_MINOR(trcidr1));

}



enum etm_impdef_type {

	ETM4_IMPDEF_HISI_CORE_COMMIT,

	ETM4_IMPDEF_FEATURE_MAX,

drivers/iio/accel/kionix-kx022a.c

+1 −1
Original line number Diff line number Diff line
@@ -864,7 +864,7 @@ static irqreturn_t kx022a_trigger_handler(int irq, void *p) 
	if (ret < 0)

		goto err_read;



	iio_push_to_buffers_with_timestamp(idev, data->buffer, pf->timestamp);

	iio_push_to_buffers_with_timestamp(idev, data->buffer, data->timestamp);

err_read:

	iio_trigger_notify_done(idev->trig);

drivers/iio/adc/ad7791.c

+1 −1
Original line number Diff line number Diff line
@@ -253,7 +253,7 @@ static const struct ad_sigma_delta_info ad7791_sigma_delta_info = { 
	.has_registers = true,

	.addr_shift = 4,

	.read_mask = BIT(3),

	.irq_flags = IRQF_TRIGGER_LOW,

	.irq_flags = IRQF_TRIGGER_FALLING,

};



static int ad7791_read_raw(struct iio_dev *indio_dev,