Commit 68cce21e authored Nov 24, 2023 by David Regan Committed by Miquel Raynal Dec 04, 2023

mtd: rawnand: NAND controller write protect



Allow NAND controller to be responsible for write protect pin
handling during fast path and exec_op destructive operation
when controller_wp flag is set.

Signed-off-by: David Regan <dregan@broadcom.com>
Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/linux-mtd/20231125012438.15191-2-dregan@broadcom.com

parent 578dc962

drivers/mtd/nand/raw/nand_base.c

+4 −0

Original line number	Diff line number	Diff line
		@@ -366,6 +366,10 @@ static int nand_check_wp(struct nand_chip *chip)
		if (chip->options & NAND_BROKEN_XD)
		return 0;

		/* controller responsible for NAND write protect */
		if (chip->controller->controller_wp)
		return 0;

		/* Check the WP bit */
		ret = nand_status_op(chip, &status);
		if (ret)

include/linux/mtd/rawnand.h

+2 −0

Original line number	Diff line number	Diff line
		@@ -1115,6 +1115,7 @@ struct nand_controller_ops {
		* the bus without restarting an entire read operation nor
		* changing the column.
		* @supported_op.cont_read: The controller supports sequential cache reads.
		* @controller_wp: the controller is in charge of handling the WP pin.
		*/
		struct nand_controller {
		struct mutex lock;
		@@ -1123,6 +1124,7 @@ struct nand_controller {
		unsigned int data_only_read: 1;
		unsigned int cont_read: 1;
		} supported_op;
		bool controller_wp;
		};

		static inline void nand_controller_init(struct nand_controller *nfc)