Commit 68d8b4f3 authored by Dave Jiang's avatar Dave Jiang
Browse files

Merge branch 'for-6.16/cxl-cleanups' into cxl-for-next 

In preparation for code changes related to AMD Zen5 address translation
support, a number of small code refactor and cleanups are send ahead.
parents 8e62ba59 98a863fe

drivers/cxl/acpi.c

+9 −1
Original line number Diff line number Diff line
@@ -419,7 +419,15 @@ static int __cxl_parse_cfmws(struct acpi_cedt_cfmws *cfmws, 
	rc = cxl_decoder_add(cxld, target_map);

	if (rc)

		return rc;

	return cxl_root_decoder_autoremove(dev, no_free_ptr(cxlrd));



	rc = cxl_root_decoder_autoremove(dev, no_free_ptr(cxlrd));

	if (rc)

		return rc;



	dev_dbg(root_port->dev.parent, "%s added to %s\n",

		dev_name(&cxld->dev), dev_name(&root_port->dev));



	return 0;

}



static int cxl_parse_cfmws(union acpi_subtable_headers *header, void *arg,

drivers/cxl/core/cdat.c

+1 −1
Original line number Diff line number Diff line
@@ -28,7 +28,7 @@ static u32 cdat_normalize(u16 entry, u64 base, u8 type) 
	 */

	if (entry == 0xffff || !entry)

		return 0;

	else if (base > (UINT_MAX / (entry)))

	if (base > (UINT_MAX / (entry)))

		return 0;



	/*

drivers/cxl/core/hdm.c

+2 −1
Original line number Diff line number Diff line
@@ -34,7 +34,8 @@ static int add_hdm_decoder(struct cxl_port *port, struct cxl_decoder *cxld, 
	if (rc)

		return rc;



	dev_dbg(&cxld->dev, "Added to port %s\n", dev_name(&port->dev));

	dev_dbg(port->uport_dev, "%s added to %s\n",

		dev_name(&cxld->dev), dev_name(&port->dev));



	return 0;

}

drivers/cxl/core/memdev.c

+2 −2
Original line number Diff line number Diff line
@@ -153,7 +153,7 @@ static ssize_t security_state_show(struct device *dev, 
		return sysfs_emit(buf, "frozen\n");

	if (state & CXL_PMEM_SEC_STATE_LOCKED)

		return sysfs_emit(buf, "locked\n");

	else



	return sysfs_emit(buf, "unlocked\n");

}

static struct device_attribute dev_attr_security_state =

drivers/cxl/core/pci.c

+31 −17
Original line number Diff line number Diff line
@@ -415,17 +415,20 @@ int cxl_hdm_decode_init(struct cxl_dev_state *cxlds, struct cxl_hdm *cxlhdm, 
	 */

	if (global_ctrl & CXL_HDM_DECODER_ENABLE || (!hdm && info->mem_enabled))

		return devm_cxl_enable_mem(&port->dev, cxlds);

	else if (!hdm)

		return -ENODEV;



	root = to_cxl_port(port->dev.parent);

	while (!is_cxl_root(root) && is_cxl_port(root->dev.parent))

		root = to_cxl_port(root->dev.parent);

	if (!is_cxl_root(root)) {

		dev_err(dev, "Failed to acquire root port for HDM enable\n");

	/*

	 * If the HDM Decoder Capability does not exist and DVSEC was

	 * not setup, the DVSEC based emulation cannot be used.

	 */

	if (!hdm)

		return -ENODEV;

	}



	/* The HDM Decoder Capability exists but is globally disabled. */



	/*

	 * If the DVSEC CXL Range registers are not enabled, just

	 * enable and use the HDM Decoder Capability registers.

	 */

	if (!info->mem_enabled) {

		rc = devm_cxl_enable_hdm(&port->dev, cxlhdm);

		if (rc)
@@ -434,6 +437,26 @@ int cxl_hdm_decode_init(struct cxl_dev_state *cxlds, struct cxl_hdm *cxlhdm, 
		return devm_cxl_enable_mem(&port->dev, cxlds);

	}



	/*

	 * Per CXL 2.0 Section 8.1.3.8.3 and 8.1.3.8.4 DVSEC CXL Range 1 Base

	 * [High,Low] when HDM operation is enabled the range register values

	 * are ignored by the device, but the spec also recommends matching the

	 * DVSEC Range 1,2 to HDM Decoder Range 0,1. So, non-zero info->ranges

	 * are expected even though Linux does not require or maintain that

	 * match. Check if at least one DVSEC range is enabled and allowed by

	 * the platform. That is, the DVSEC range must be covered by a locked

	 * platform window (CFMWS). Fail otherwise as the endpoint's decoders

	 * cannot be used.

	 */



	root = to_cxl_port(port->dev.parent);

	while (!is_cxl_root(root) && is_cxl_port(root->dev.parent))

		root = to_cxl_port(root->dev.parent);

	if (!is_cxl_root(root)) {

		dev_err(dev, "Failed to acquire root port for HDM enable\n");

		return -ENODEV;

	}



	for (i = 0, allowed = 0; i < info->ranges; i++) {

		struct device *cxld_dev;
@@ -453,15 +476,6 @@ int cxl_hdm_decode_init(struct cxl_dev_state *cxlds, struct cxl_hdm *cxlhdm, 
		return -ENXIO;

	}



	/*

	 * Per CXL 2.0 Section 8.1.3.8.3 and 8.1.3.8.4 DVSEC CXL Range 1 Base

	 * [High,Low] when HDM operation is enabled the range register values

	 * are ignored by the device, but the spec also recommends matching the

	 * DVSEC Range 1,2 to HDM Decoder Range 0,1. So, non-zero info->ranges

	 * are expected even though Linux does not require or maintain that

	 * match. If at least one DVSEC range is enabled and allowed, skip HDM

	 * Decoder Capability Enable.

	 */

	return 0;

}

EXPORT_SYMBOL_NS_GPL(cxl_hdm_decode_init, "CXL");