Commit 68e61f6f authored by Sean Christopherson's avatar Sean Christopherson
Browse files

KVM: SVM: Emulate PERF_CNTR_GLOBAL_STATUS_SET for PerfMonV2 

Emulate PERF_CNTR_GLOBAL_STATUS_SET when PerfMonV2 is enumerated to the
guest, as the MSR is supposed to exist in all AMD v2 PMUs.

Fixes: 4a277189 ("KVM: x86/svm/pmu: Add AMD PerfMonV2 support")
Cc: stable@vger.kernel.org
Cc: Sandipan Das <sandipan.das@amd.com>
Link: https://lore.kernel.org/r/20250711172746.1579423-1-seanjc@google.com


Signed-off-by: default avatarSean Christopherson <seanjc@google.com>
parent e750f853

arch/x86/include/asm/msr-index.h

+1 −0
Original line number Diff line number Diff line
@@ -733,6 +733,7 @@ 
#define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS	0xc0000300

#define MSR_AMD64_PERF_CNTR_GLOBAL_CTL		0xc0000301

#define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR	0xc0000302

#define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_SET	0xc0000303



/* AMD Hardware Feedback Support MSRs */

#define MSR_AMD_WORKLOAD_CLASS_CONFIG		0xc0000500

arch/x86/kvm/pmu.c

+5 −0
Original line number Diff line number Diff line
@@ -650,6 +650,7 @@ int kvm_pmu_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 
		msr_info->data = pmu->global_ctrl;

		break;

	case MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR:

	case MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_SET:

	case MSR_CORE_PERF_GLOBAL_OVF_CTRL:

		msr_info->data = 0;

		break;
@@ -711,6 +712,10 @@ int kvm_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 
		if (!msr_info->host_initiated)

			pmu->global_status &= ~data;

		break;

	case MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_SET:

		if (!msr_info->host_initiated)

			pmu->global_status |= data & ~pmu->global_status_rsvd;

		break;

	default:

		kvm_pmu_mark_pmc_in_use(vcpu, msr_info->index);

		return kvm_pmu_call(set_msr)(vcpu, msr_info);

arch/x86/kvm/svm/pmu.c

+1 −0
Original line number Diff line number Diff line
@@ -113,6 +113,7 @@ static bool amd_is_valid_msr(struct kvm_vcpu *vcpu, u32 msr) 
	case MSR_AMD64_PERF_CNTR_GLOBAL_STATUS:

	case MSR_AMD64_PERF_CNTR_GLOBAL_CTL:

	case MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR:

	case MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_SET:

		return pmu->version > 1;

	default:

		if (msr > MSR_F15H_PERF_CTR5 &&

arch/x86/kvm/x86.c

+2 −0
Original line number Diff line number Diff line
@@ -367,6 +367,7 @@ static const u32 msrs_to_save_pmu[] = { 
	MSR_AMD64_PERF_CNTR_GLOBAL_CTL,

	MSR_AMD64_PERF_CNTR_GLOBAL_STATUS,

	MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR,

	MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_SET,

};



static u32 msrs_to_save[ARRAY_SIZE(msrs_to_save_base) +
@@ -7353,6 +7354,7 @@ static void kvm_probe_msr_to_save(u32 msr_index) 
	case MSR_AMD64_PERF_CNTR_GLOBAL_CTL:

	case MSR_AMD64_PERF_CNTR_GLOBAL_STATUS:

	case MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR:

	case MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_SET:

		if (!kvm_cpu_cap_has(X86_FEATURE_PERFMON_V2))

			return;

		break;