Unverified Commit 68fdf2c9 authored by Gustavo Sousa's avatar Gustavo Sousa Committed by Rodrigo Vivi
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drm/xe/xe3p_lpg: Add missing indirect ring state feature flag 



Even though commit 8fcb7dfb ("drm/xe/xe3p_lpg: Add support for
graphics IP 35.10") mentions that the support for Indirect Ring State
exists for Xe3p_LPG, it missed actually setting the feature flag in
graphics_xe3p_lpg.  Fix that by adding the missing member.

Fixes: 8fcb7dfb ("drm/xe/xe3p_lpg: Add support for graphics IP 35.10")
Reviewed-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Link: https://patch.msgid.link/20260401-xe3p_lpg-indirect-ring-state-v1-1-0e4b5edf6898@intel.com


Signed-off-by: default avatarGustavo Sousa <gustavo.sousa@intel.com>
(cherry picked from commit ec4f4970eb744fd7d6d135f40f5c83bd05982e72)
Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
parent 9d7ca81b

drivers/gpu/drm/xe/xe_pci.c

+1 −0
Original line number Diff line number Diff line
@@ -118,6 +118,7 @@ static const struct xe_graphics_desc graphics_xe2 = { 


static const struct xe_graphics_desc graphics_xe3p_lpg = {

	XE2_GFX_FEATURES,

	.has_indirect_ring_state = 1,

	.multi_queue_engine_class_mask = BIT(XE_ENGINE_CLASS_COPY) | BIT(XE_ENGINE_CLASS_COMPUTE),

	.num_geometry_xecore_fuse_regs = 3,

	.num_compute_xecore_fuse_regs = 3,