Commit 69541898 authored by Jason Gunthorpe's avatar Jason Gunthorpe Committed by Joerg Roedel
Browse files

iommu/riscv: Enable SVNAPOT support for contiguous ptes 



This turns on a 64k page size. The "RISC-V IOMMU Architecture
Specification" states:

  6.4 IOMMU capabilities
  [..]
  IOMMU implementations must support the Svnapot standard extension for
  NAPOT Translation Contiguity.

So just switch it on unconditionally.

Cc: Xu Lu <luxu.kernel@bytedance.com>
Tested-by: default avatarVincent Chen <vincent.chen@sifive.com>
Acked-by: Paul Walmsley <pjw@kernel.org> # arch/riscv
Reviewed-by: default avatarTomasz Jeznach <tjeznach@rivosinc.com>
Tested-by: default avatarTomasz Jeznach <tjeznach@rivosinc.com>
Signed-off-by: default avatarJason Gunthorpe <jgg@nvidia.com>
Signed-off-by: default avatarJoerg Roedel <joerg.roedel@amd.com>
parent e5ef3219

drivers/iommu/riscv/iommu.c

+6 −1
Original line number Diff line number Diff line
@@ -1185,8 +1185,13 @@ static struct iommu_domain *riscv_iommu_alloc_paging_domain(struct device *dev) 


	INIT_LIST_HEAD_RCU(&domain->bonds);

	spin_lock_init(&domain->lock);

	/*

	 * 6.4 IOMMU capabilities [..] IOMMU implementations must support the

	 * Svnapot standard extension for NAPOT Translation Contiguity.

	 */

	cfg.common.features = BIT(PT_FEAT_SIGN_EXTEND) |

			      BIT(PT_FEAT_FLUSH_RANGE);

			      BIT(PT_FEAT_FLUSH_RANGE) |

			      BIT(PT_FEAT_RISCV_SVNAPOT_64K);

	domain->riscvpt.iommu.nid = dev_to_node(iommu->dev);

	domain->domain.ops = &riscv_iommu_paging_domain_ops;