Commit 69684376 authored by Alexander Duyck's avatar Alexander Duyck Committed by Jakub Kicinski
Browse files

eth: fbnic: Add link detection 



Add basic support for detecting the link and reporting it at the netdev
layer. For now we will just use the values reporeted by the firmware as the
link configuration and assume that is the current configuration of the MAC
and PCS.

With this we start the stubbing out of the phylink interface that will be
used to provide the configuration interface for ethtool in a future patch
set.

The phylink interface isn't an exact fit. As such we are currently working
around several issues in this patch set that we plan to address in the
future such as:
1. Support for FEC
2. Support for multiple lanes to handle 50GbaseR2 vs 50GbaseR1
3. Support for BMC

CC: Russell King <linux@armlinux.org.uk>
CC: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: default avatarAlexander Duyck <alexanderduyck@fb.com>
Link: https://patch.msgid.link/172079939835.1778861.5964790909718481811.stgit@ahduyck-xeon-server.home.arpa


Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parent 20d2e88c

drivers/net/ethernet/meta/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -21,6 +21,7 @@ config FBNIC 
	tristate "Meta Platforms Host Network Interface"

	depends on X86_64 || COMPILE_TEST

	depends on PCI_MSI

	select PHYLINK

	help

	  This driver supports Meta Platforms Host Network Interface.

drivers/net/ethernet/meta/fbnic/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -13,5 +13,6 @@ fbnic-y := fbnic_devlink.o \ 
	   fbnic_mac.o \

	   fbnic_netdev.o \

	   fbnic_pci.o \

	   fbnic_phylink.o \

	   fbnic_tlv.o \

	   fbnic_txrx.o

drivers/net/ethernet/meta/fbnic/fbnic.h

+10 −0
Original line number Diff line number Diff line
@@ -21,6 +21,7 @@ struct fbnic_dev { 
	u32 __iomem *uc_addr4;

	const struct fbnic_mac *mac;

	unsigned int fw_msix_vector;

	unsigned int pcs_msix_vector;

	unsigned short num_irqs;



	struct delayed_work service_task;
@@ -49,6 +50,7 @@ struct fbnic_dev { 
 */

enum {

	FBNIC_FW_MSIX_ENTRY,

	FBNIC_PCS_MSIX_ENTRY,

	FBNIC_NON_NAPI_VECTORS

};
@@ -95,6 +97,11 @@ void fbnic_fw_wr32(struct fbnic_dev *fbd, u32 reg, u32 val); 
#define fw_wr32(_f, _r, _v)	fbnic_fw_wr32(_f, _r, _v)

#define fw_wrfl(_f)		fbnic_fw_rd32(_f, FBNIC_FW_ZERO_REG)



static inline bool fbnic_bmc_present(struct fbnic_dev *fbd)

{

	return fbd->fw_cap.bmc_present;

}



static inline bool fbnic_init_failure(struct fbnic_dev *fbd)

{

	return !fbd->netdev;
@@ -110,6 +117,9 @@ void fbnic_devlink_unregister(struct fbnic_dev *fbd); 
int fbnic_fw_enable_mbx(struct fbnic_dev *fbd);

void fbnic_fw_disable_mbx(struct fbnic_dev *fbd);



int fbnic_pcs_irq_enable(struct fbnic_dev *fbd);

void fbnic_pcs_irq_disable(struct fbnic_dev *fbd);



int fbnic_request_irq(struct fbnic_dev *dev, int nr, irq_handler_t handler,

		      unsigned long flags, const char *name, void *data);

void fbnic_free_irq(struct fbnic_dev *dev, int nr, void *data);

drivers/net/ethernet/meta/fbnic/fbnic_csr.h

+39 −0
Original line number Diff line number Diff line
@@ -85,6 +85,9 @@ 
#define FBNIC_INTR_MSIX_CTRL(n)		(0x00040 + (n)) /* 0x00100 + 4*n */

#define FBNIC_INTR_MSIX_CTRL_VECTOR_MASK	CSR_GENMASK(7, 0)

#define FBNIC_INTR_MSIX_CTRL_ENABLE		CSR_BIT(31)

enum {

	FBNIC_INTR_MSIX_CTRL_PCS_IDX	= 34,

};



#define FBNIC_CSR_END_INTR		0x0005f	/* CSR section delimiter */
@@ -419,6 +422,42 @@ enum { 
#define FBNIC_MASTER_SPARE_0		0x0C41B		/* 0x3106c */

#define FBNIC_CSR_END_MASTER		0x0C452	/* CSR section delimiter */



/* MAC MAC registers (ASIC only) */

#define FBNIC_CSR_START_MAC_MAC		0x11000 /* CSR section delimiter */

#define FBNIC_MAC_COMMAND_CONFIG	0x11002		/* 0x44008 */

#define FBNIC_MAC_COMMAND_CONFIG_RX_PAUSE_DIS	CSR_BIT(29)

#define FBNIC_MAC_COMMAND_CONFIG_TX_PAUSE_DIS	CSR_BIT(28)

#define FBNIC_MAC_COMMAND_CONFIG_FLT_HDL_DIS	CSR_BIT(27)

#define FBNIC_MAC_COMMAND_CONFIG_TX_PAD_EN	CSR_BIT(11)

#define FBNIC_MAC_COMMAND_CONFIG_LOOPBACK_EN	CSR_BIT(10)

#define FBNIC_MAC_COMMAND_CONFIG_PROMISC_EN	CSR_BIT(4)

#define FBNIC_MAC_COMMAND_CONFIG_RX_ENA		CSR_BIT(1)

#define FBNIC_MAC_COMMAND_CONFIG_TX_ENA		CSR_BIT(0)

#define FBNIC_MAC_CL01_PAUSE_QUANTA	0x11015		/* 0x44054 */

#define FBNIC_MAC_CL01_QUANTA_THRESH	0x11019		/* 0x44064 */

#define FBNIC_CSR_END_MAC_MAC		0x11028 /* CSR section delimiter */



/* Signals from MAC, AN, PCS, and LED CSR registers (ASIC only) */

#define FBNIC_CSR_START_SIG		0x11800 /* CSR section delimiter */

#define FBNIC_SIG_MAC_IN0		0x11800		/* 0x46000 */

#define FBNIC_SIG_MAC_IN0_RESET_FF_TX_CLK	CSR_BIT(14)

#define FBNIC_SIG_MAC_IN0_RESET_FF_RX_CLK	CSR_BIT(13)

#define FBNIC_SIG_MAC_IN0_RESET_TX_CLK		CSR_BIT(12)

#define FBNIC_SIG_MAC_IN0_RESET_RX_CLK		CSR_BIT(11)

#define FBNIC_SIG_MAC_IN0_TX_CRC		CSR_BIT(8)

#define FBNIC_SIG_MAC_IN0_CFG_MODE128		CSR_BIT(10)

#define FBNIC_SIG_PCS_OUT0		0x11808		/* 0x46020 */

#define FBNIC_SIG_PCS_OUT0_LINK			CSR_BIT(27)

#define FBNIC_SIG_PCS_OUT0_BLOCK_LOCK		CSR_GENMASK(24, 5)

#define FBNIC_SIG_PCS_OUT0_AMPS_LOCK		CSR_GENMASK(4, 1)

#define FBNIC_SIG_PCS_OUT1		0x11809		/* 0x46024 */

#define FBNIC_SIG_PCS_OUT1_FCFEC_LOCK		CSR_GENMASK(11, 8)

#define FBNIC_SIG_PCS_INTR_STS		0x11814		/* 0x46050 */

#define FBNIC_SIG_PCS_INTR_LINK_DOWN		CSR_BIT(1)

#define FBNIC_SIG_PCS_INTR_LINK_UP		CSR_BIT(0)

#define FBNIC_SIG_PCS_INTR_MASK		0x11816		/* 0x46058 */

#define FBNIC_CSR_END_SIG		0x1184e /* CSR section delimiter */



/* PUL User Registers */

#define FBNIC_CSR_START_PUL_USER	0x31000	/* CSR section delimiter */

#define FBNIC_PUL_OB_TLP_HDR_AW_CFG	0x3103d		/* 0xc40f4 */

drivers/net/ethernet/meta/fbnic/fbnic_fw.h

+13 −0
Original line number Diff line number Diff line
@@ -104,6 +104,19 @@ enum { 
	FBNIC_FW_CAP_RESP_MSG_MAX

};



enum {

	FBNIC_FW_LINK_SPEED_25R1		= 1,

	FBNIC_FW_LINK_SPEED_50R2		= 2,

	FBNIC_FW_LINK_SPEED_50R1		= 3,

	FBNIC_FW_LINK_SPEED_100R2		= 4,

};



enum {

	FBNIC_FW_LINK_FEC_NONE			= 1,

	FBNIC_FW_LINK_FEC_RS			= 2,

	FBNIC_FW_LINK_FEC_BASER			= 3,

};



enum {

	FBNIC_FW_OWNERSHIP_FLAG			= 0x0,

	FBNIC_FW_OWNERSHIP_MSG_MAX