Commit 6977c89b authored by Geert Uytterhoeven's avatar Geert Uytterhoeven
Browse files

Merge tag 'renesas-r9a09g047-dt-binding-defs-tag1' into renesas-dts-for-v6.14 

Renesas RZ/G3E DT Binding Definitions

DT bindings and binding definitions for the Renesas RZ/G3E (R9A09G047)
SoC, shared by driver and DT source files.
parents a57e6e1f 25458fdd

Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml

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@@ -4,19 +4,22 @@ 
$id: http://devicetree.org/schemas/clock/renesas,rzv2h-cpg.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Renesas RZ/V2H(P) Clock Pulse Generator (CPG)

title: Renesas RZ/{G3E,V2H(P)} Clock Pulse Generator (CPG)



maintainers:

  - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>



description:

  On Renesas RZ/V2H(P) SoCs, the CPG (Clock Pulse Generator) handles generation

  and control of clock signals for the IP modules, generation and control of resets,

  and control over booting, low power consumption and power supply domains.

  On Renesas RZ/{G3E,V2H(P)} SoCs, the CPG (Clock Pulse Generator) handles

  generation and control of clock signals for the IP modules, generation and

  control of resets, and control over booting, low power consumption and power

  supply domains.



properties:

  compatible:

    const: renesas,r9a09g057-cpg

    enum:

      - renesas,r9a09g047-cpg # RZ/G3E

      - renesas,r9a09g057-cpg # RZ/V2H



  reg:

    maxItems: 1
@@ -37,7 +40,7 @@ properties: 
    description: |

      - For CPG core clocks, the two clock specifier cells must be "CPG_CORE"

        and a core clock reference, as defined in

        <dt-bindings/clock/renesas,r9a09g057-cpg.h>,

        <dt-bindings/clock/renesas,r9a09g0*-cpg.h>,

      - For module clocks, the two clock specifier cells must be "CPG_MOD" and

        a module number.  The module number is calculated as the CLKON register

        offset index multiplied by 16, plus the actual bit in the register

Documentation/devicetree/bindings/soc/renesas/renesas.yaml

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@@ -527,6 +527,23 @@ properties: 
              - renesas,rzv2mevk2   # RZ/V2M Eval Board v2.0

          - const: renesas,r9a09g011



      - description: RZ/G3E (R9A09G047)

        items:

          - enum:

              - renesas,smarc2-evk # RZ SMARC Carrier-II EVK

          - enum:

              - renesas,rzg3e-smarcm # RZ/G3E SMARC Module (SoM)

          - enum:

              - renesas,r9a09g047e27 # Dual Cortex-A55 + Cortex-M33 (15mm BGA)

              - renesas,r9a09g047e28 # Dual Cortex-A55 + Cortex-M33 (21mm BGA)

              - renesas,r9a09g047e37 # Dual Cortex-A55 + Cortex-M33 + Ethos-U55 (15mm BGA)

              - renesas,r9a09g047e38 # Dual Cortex-A55 + Cortex-M33 + Ethos-U55 (21mm BGA)

              - renesas,r9a09g047e47 # Quad Cortex-A55 + Cortex-M33 (15mm BGA)

              - renesas,r9a09g047e48 # Quad Cortex-A55 + Cortex-M33 (21mm BGA)

              - renesas,r9a09g047e57 # Quad Cortex-A55 + Cortex-M33 + Ethos-U55 (15mm BGA)

              - renesas,r9a09g047e58 # Quad Cortex-A55 + Cortex-M33 + Ethos-U55 (21mm BGA)

          - const: renesas,r9a09g047



      - description: RZ/V2H(P) (R9A09G057)

        items:

          - enum:

include/dt-bindings/clock/renesas,r9a09g047-cpg.h

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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

 *

 * Copyright (C) 2024 Renesas Electronics Corp.

 */

#ifndef __DT_BINDINGS_CLOCK_RENESAS_R9A09G047_CPG_H__

#define __DT_BINDINGS_CLOCK_RENESAS_R9A09G047_CPG_H__



#include <dt-bindings/clock/renesas-cpg-mssr.h>



/* Core Clock list */

#define R9A09G047_SYS_0_PCLK			0

#define R9A09G047_CA55_0_CORECLK0		1

#define R9A09G047_CA55_0_CORECLK1		2

#define R9A09G047_CA55_0_CORECLK2		3

#define R9A09G047_CA55_0_CORECLK3		4

#define R9A09G047_CA55_0_PERIPHCLK		5

#define R9A09G047_CM33_CLK0			6

#define R9A09G047_CST_0_SWCLKTCK		7

#define R9A09G047_IOTOP_0_SHCLK			8



#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G047_CPG_H__ */