Commit 697cb5cc authored by Boyuan Zhang's avatar Boyuan Zhang Committed by Alex Deucher
Browse files

drm/amd/pm: add inst to set_powergating_by_smu



Add an instance parameter to set_powergating_by_smu() function, and
re-write all amd_pm functions accordingly. Then use the instance to
call smu_dpm_set_vcn_enable().

v2: remove duplicated functions.

remove for-loop in smu_dpm_set_power_gate(), and temporarily move it to
to amdgpu_dpm_set_powergating_by_smu(), in order to keep the exact same
logic as before, until further separation in next patch.

v3: add instance number in error message.

Signed-off-by: default avatarBoyuan Zhang <boyuan.zhang@amd.com>
Acked-by: default avatarChristian König <christian.koenig@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 15df736a
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+3 −1
Original line number Diff line number Diff line
@@ -421,7 +421,9 @@ struct amd_pm_funcs {
	int (*load_firmware)(void *handle);
	int (*wait_for_fw_loading_complete)(void *handle);
	int (*set_powergating_by_smu)(void *handle,
				uint32_t block_type, bool gate);
				uint32_t block_type,
				bool gate,
				int inst);
	int (*set_clockgating_by_smu)(void *handle, uint32_t msg_id);
	int (*set_power_limit)(void *handle, uint32_t n);
	int (*get_power_limit)(void *handle, uint32_t *limit,
+8 −2
Original line number Diff line number Diff line
@@ -88,7 +88,6 @@ int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev, uint32_t block
	case AMD_IP_BLOCK_TYPE_UVD:
	case AMD_IP_BLOCK_TYPE_VCE:
	case AMD_IP_BLOCK_TYPE_GFX:
	case AMD_IP_BLOCK_TYPE_VCN:
	case AMD_IP_BLOCK_TYPE_SDMA:
	case AMD_IP_BLOCK_TYPE_JPEG:
	case AMD_IP_BLOCK_TYPE_GMC:
@@ -96,7 +95,14 @@ int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev, uint32_t block
	case AMD_IP_BLOCK_TYPE_VPE:
		if (pp_funcs && pp_funcs->set_powergating_by_smu)
			ret = (pp_funcs->set_powergating_by_smu(
				(adev)->powerplay.pp_handle, block_type, gate));
				(adev)->powerplay.pp_handle, block_type, gate, 0));
		break;
	case AMD_IP_BLOCK_TYPE_VCN:
		if (pp_funcs && pp_funcs->set_powergating_by_smu) {
			for (int i = 0; i < adev->vcn.num_vcn_inst; i++)
				ret = (pp_funcs->set_powergating_by_smu(
					(adev)->powerplay.pp_handle, block_type, gate, i));
		}
		break;
	default:
		break;
+3 −1
Original line number Diff line number Diff line
@@ -3276,7 +3276,9 @@ static int kv_dpm_read_sensor(void *handle, int idx,
}

static int kv_set_powergating_by_smu(void *handle,
				uint32_t block_type, bool gate)
				uint32_t block_type,
				bool gate,
				int inst)
{
	switch (block_type) {
	case AMD_IP_BLOCK_TYPE_UVD:
+3 −1
Original line number Diff line number Diff line
@@ -1227,7 +1227,9 @@ static void pp_dpm_powergate_sdma(void *handle, bool gate)
}

static int pp_set_powergating_by_smu(void *handle,
				uint32_t block_type, bool gate)
				uint32_t block_type,
				bool gate,
				int inst)
{
	int ret = 0;

+7 −9
Original line number Diff line number Diff line
@@ -358,11 +358,11 @@ static int smu_set_mall_enable(struct smu_context *smu)
 */
static int smu_dpm_set_power_gate(void *handle,
				  uint32_t block_type,
				  bool gate)
				  bool gate,
				  int inst)
{
	struct smu_context *smu = handle;
	struct amdgpu_device *adev = smu->adev;
	int i, ret = 0;
	int ret = 0;

	if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) {
		dev_WARN(smu->adev->dev,
@@ -378,12 +378,10 @@ static int smu_dpm_set_power_gate(void *handle,
	 */
	case AMD_IP_BLOCK_TYPE_UVD:
	case AMD_IP_BLOCK_TYPE_VCN:
		for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
			ret = smu_dpm_set_vcn_enable(smu, !gate, i);
		ret = smu_dpm_set_vcn_enable(smu, !gate, inst);
		if (ret)
			dev_err(smu->adev->dev, "Failed to power %s VCN instance %d!\n",
					gate ? "gate" : "ungate", i);
		}
				gate ? "gate" : "ungate", inst);
		break;
	case AMD_IP_BLOCK_TYPE_GFX:
		ret = smu_gfx_off_control(smu, gate);