Commit 69a46ce1 authored by Tom Chung's avatar Tom Chung Committed by Alex Deucher
Browse files

drm/amd/display: Do not enable Replay and PSR while VRR is on in amdgpu_dm_commit_planes() 



[Why]
Replay and PSR will cause some video corruption while VRR is enabled.

[How]
Do not enable the Replay and PSR while VRR is active in
amdgpu_dm_enable_self_refresh().

Fixes: 67edb81d ("drm/amd/display: Disable replay and psr while VRR is enabled")
Reviewed-by: default avatarSun peng Li <sunpeng.li@amd.com>
Signed-off-by: default avatarTom Chung <chiahsuan.chung@amd.com>
Signed-off-by: default avatarFangzhi Zuo <jerry.zuo@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
parent ba6d8f87

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c

+4 −2
Original line number Diff line number Diff line
@@ -113,6 +113,7 @@ bool amdgpu_dm_crtc_vrr_active(const struct dm_crtc_state *dm_state) 
 *

 * Panel Replay and PSR SU

 * - Enable when:

 *      - VRR is disabled

 *      - vblank counter is disabled

 *      - entry is allowed: usermode demonstrates an adequate number of fast

 *        commits)
@@ -131,19 +132,20 @@ static void amdgpu_dm_crtc_set_panel_sr_feature( 
	bool is_sr_active = (link->replay_settings.replay_allow_active ||

				 link->psr_settings.psr_allow_active);

	bool is_crc_window_active = false;

	bool vrr_active = amdgpu_dm_crtc_vrr_active_irq(vblank_work->acrtc);



#ifdef CONFIG_DRM_AMD_SECURE_DISPLAY

	is_crc_window_active =

		amdgpu_dm_crc_window_is_activated(&vblank_work->acrtc->base);

#endif



	if (link->replay_settings.replay_feature_enabled &&

	if (link->replay_settings.replay_feature_enabled && !vrr_active &&

		allow_sr_entry && !is_sr_active && !is_crc_window_active) {

		amdgpu_dm_replay_enable(vblank_work->stream, true);

	} else if (vblank_enabled) {

		if (link->psr_settings.psr_version < DC_PSR_VERSION_SU_1 && is_sr_active)

			amdgpu_dm_psr_disable(vblank_work->stream, false);

	} else if (link->psr_settings.psr_feature_enabled &&

	} else if (link->psr_settings.psr_feature_enabled && !vrr_active &&

		allow_sr_entry && !is_sr_active && !is_crc_window_active) {



		struct amdgpu_dm_connector *aconn =