Commit 69b79e80 authored by Rob Clark's avatar Rob Clark
Browse files

drm/msm/a6xx: Cleanup indexed regs const'ness 



These tables were made non-const in commit 3cba4a2c ("drm/msm/a6xx:
Update ROQ size in coredump") in order to avoid powering up the GPU when
reading back a devcoredump.  Instead let's just stash the count that is
potentially read from hw in struct a6xx_gpu_state_obj, and make the
tables const again.

Signed-off-by: default avatarRob Clark <robdclark@chromium.org>
Patchwork: https://patchwork.freedesktop.org/patch/592699/
parent f3f8207d

drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c

+9 −6
Original line number Diff line number Diff line
@@ -24,6 +24,7 @@ 
struct a6xx_gpu_state_obj {

	const void *handle;

	u32 *data;

	u32 count;	/* optional, used when count potentially read from hw */

};



struct a6xx_gpu_state {
@@ -1437,16 +1438,18 @@ static u32 a7xx_get_cp_roq_size(struct msm_gpu *gpu) 
/* Read a block of data from an indexed register pair */

static void a6xx_get_indexed_regs(struct msm_gpu *gpu,

		struct a6xx_gpu_state *a6xx_state,

		struct a6xx_indexed_registers *indexed,

		const struct a6xx_indexed_registers *indexed,

		struct a6xx_gpu_state_obj *obj)

{

	u32 count = indexed->count;

	int i;



	obj->handle = (const void *) indexed;

	if (indexed->count_fn)

		indexed->count = indexed->count_fn(gpu);

		count = indexed->count_fn(gpu);



	obj->data = state_kcalloc(a6xx_state, indexed->count, sizeof(u32));

	obj->data = state_kcalloc(a6xx_state, count, sizeof(u32));

	obj->count = count;

	if (!obj->data)

		return;
@@ -1454,7 +1457,7 @@ static void a6xx_get_indexed_regs(struct msm_gpu *gpu, 
	gpu_write(gpu, indexed->addr, 0);



	/* Read the data - each read increments the internal address by 1 */

	for (i = 0; i < indexed->count; i++)

	for (i = 0; i < count; i++)

		obj->data[i] = gpu_read(gpu, indexed->data);

}
@@ -1890,9 +1893,9 @@ static void a6xx_show_indexed_regs(struct a6xx_gpu_state_obj *obj, 
		return;



	print_name(p, "  - regs-name: ", indexed->name);

	drm_printf(p, "    dwords: %d\n", indexed->count);

	drm_printf(p, "    dwords: %d\n", obj->count);



	print_ascii85(p, indexed->count << 2, obj->data);

	print_ascii85(p, obj->count << 2, obj->data);

}



static void a6xx_show_debugbus_block(const struct a6xx_debugbus_block *block,

drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h

+4 −4
Original line number Diff line number Diff line
@@ -397,7 +397,7 @@ struct a6xx_indexed_registers { 
	u32 (*count_fn)(struct msm_gpu *gpu);

};



static struct a6xx_indexed_registers a6xx_indexed_reglist[] = {

static const struct a6xx_indexed_registers a6xx_indexed_reglist[] = {

	{ "CP_SQE_STAT", REG_A6XX_CP_SQE_STAT_ADDR,

		REG_A6XX_CP_SQE_STAT_DATA, 0x33, NULL },

	{ "CP_DRAW_STATE", REG_A6XX_CP_DRAW_STATE_ADDR,
@@ -408,7 +408,7 @@ static struct a6xx_indexed_registers a6xx_indexed_reglist[] = { 
		REG_A6XX_CP_ROQ_DBG_DATA, 0, a6xx_get_cp_roq_size},

};



static struct a6xx_indexed_registers a7xx_indexed_reglist[] = {

static const struct a6xx_indexed_registers a7xx_indexed_reglist[] = {

	{ "CP_SQE_STAT", REG_A6XX_CP_SQE_STAT_ADDR,

		REG_A6XX_CP_SQE_STAT_DATA, 0x33, NULL },

	{ "CP_DRAW_STATE", REG_A6XX_CP_DRAW_STATE_ADDR,
@@ -433,12 +433,12 @@ static struct a6xx_indexed_registers a7xx_indexed_reglist[] = { 
		REG_A6XX_CP_ROQ_DBG_DATA, 0, a7xx_get_cp_roq_size },

};



static struct a6xx_indexed_registers a6xx_cp_mempool_indexed = {

static const struct a6xx_indexed_registers a6xx_cp_mempool_indexed = {

	"CP_MEMPOOL", REG_A6XX_CP_MEM_POOL_DBG_ADDR,

		REG_A6XX_CP_MEM_POOL_DBG_DATA, 0x2060, NULL,

};



static struct a6xx_indexed_registers a7xx_cp_bv_mempool_indexed[] = {

static const struct a6xx_indexed_registers a7xx_cp_bv_mempool_indexed[] = {

	{ "CP_MEMPOOL", REG_A6XX_CP_MEM_POOL_DBG_ADDR,

		REG_A6XX_CP_MEM_POOL_DBG_DATA, 0x2100, NULL },

	{ "CP_BV_MEMPOOL", REG_A7XX_CP_BV_MEM_POOL_DBG_ADDR,