Unverified Commit 6a42bc97 authored by Tudor Ambarus's avatar Tudor Ambarus
Browse files

mtd: spi-nor: core: Allow specifying the byte order in Octal DTR mode 



Macronix swaps bytes on a 16-bit boundary when configured in Octal DTR.
The byte order of 16-bit words is swapped when read or written in 8D-8D-8D
mode compared to STR modes. Allow operations to specify the byte order in
DTR mode, so that controllers can swap the bytes back at run-time to
address the flash's endianness requirements, if they are capable. If the
controller is not capable of swapping the bytes, the protocol is downgrade
via spi_nor_spimem_adjust_hwcaps(). When available, the swapping of the
bytes is always done regardless if it's a data or register access, so that
it comply with the JESD216 requirements: "Byte order of 16-bit words is
swapped when read in 8D-8D-8D mode compared to 1-1-1".

Merge Tudor's patch and add modifications for suiting newer version
of Linux kernel.

Suggested-by: default avatarMichael Walle <mwalle@kernel.org>
Signed-off-by: default avatarJaimeLiao <jaimeliao@mxic.com.tw>
Signed-off-by: default avatarAlvinZhou <alvinzhou@mxic.com.tw>
Link: https://lore.kernel.org/r/20240926141956.2386374-4-alvinzhou.tw@gmail.com


Signed-off-by: default avatarTudor Ambarus <tudor.ambarus@linaro.org>
parent ccac858d

drivers/mtd/spi-nor/core.c

+3 −0
Original line number Diff line number Diff line
@@ -113,6 +113,9 @@ void spi_nor_spimem_setup_op(const struct spi_nor *nor, 
		op->cmd.opcode = (op->cmd.opcode << 8) | ext;

		op->cmd.nbytes = 2;

	}



	if (proto == SNOR_PROTO_8_8_8_DTR && nor->flags & SNOR_F_SWAP16)

		op->data.swap16 = true;

}



/**

drivers/mtd/spi-nor/core.h

+1 −0
Original line number Diff line number Diff line
@@ -140,6 +140,7 @@ enum spi_nor_option_flags { 
	SNOR_F_RWW		= BIT(14),

	SNOR_F_ECC		= BIT(15),

	SNOR_F_NO_WP		= BIT(16),

	SNOR_F_SWAP16		= BIT(17),

};



struct spi_nor_read_command {