Commit 6a5d95b0 authored by Tim Harvey's avatar Tim Harvey Committed by Shawn Guo
Browse files

arm64: dts: imx8mp-venice-gw74xx: add M2SKT_GPIO10 gpio configuration 



The GW74xx D revision has added a M2SKT_GPIO10 GPIO which routes to the
GPIO10 pin of the M.2 socket for compatibility with certain devices.

Add the iomux and a line name for this.

Signed-off-by: default avatarTim Harvey <tharvey@gateworks.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent b98e1aa9

arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts

+2 −1
Original line number Diff line number Diff line
@@ -299,7 +299,7 @@ &gpio2 { 
&gpio3 {

	gpio-line-names =

		"", "", "", "", "", "", "m2_rst", "",

		"", "", "", "", "", "", "", "",

		"", "", "", "", "", "", "m2_gpio10", "",

		"", "", "", "", "", "", "", "",

		"", "", "", "", "", "", "", "";

};
@@ -816,6 +816,7 @@ MX8MP_IOMUXC_SD2_CLK__GPIO2_IO13 0x40000150 /* PCIE1_WDIS# */ 
			MX8MP_IOMUXC_SD2_CMD__GPIO2_IO14	0x40000150 /* PCIE3_WDIS# */

			MX8MP_IOMUXC_SD2_DATA3__GPIO2_IO18	0x40000150 /* PCIE2_WDIS# */

			MX8MP_IOMUXC_NAND_DATA00__GPIO3_IO06	0x40000040 /* M2SKT_RST# */

			MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14	0x40000040 /* M2SKT_GPIO10 */

			MX8MP_IOMUXC_SAI3_TXD__GPIO5_IO01	0x40000104 /* UART_TERM */

			MX8MP_IOMUXC_SAI3_TXFS__GPIO4_IO31	0x40000104 /* UART_RS485 */

			MX8MP_IOMUXC_SAI3_TXC__GPIO5_IO00	0x40000104 /* UART_HALF */