Commit 6a652f6d authored by Charlene Liu's avatar Charlene Liu Committed by Alex Deucher
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drm/amd/display: Add warmup escape call support 



Add warmup escape support, for diags, in a way that is possible to
choose a new or an existing sequence. For achieving this goal, this
commit adds separated MCIF buffer as VCN request.

Signed-off-by: default avatarCharlene Liu <charlene.liu@amd.com>
Reviewed-by: default avatarChris Park <Chris.Park@amd.com>
Acked-by: default avatarRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent d87dedb1

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

+37 −22
Original line number Diff line number Diff line
@@ -406,6 +406,12 @@ bool dc_stream_add_writeback(struct dc *dc, 
		stream->writeback_info[stream->num_wb_info++] = *wb_info;

	}



	if (dc->hwss.enable_writeback) {

		struct dc_stream_status *stream_status = dc_stream_get_status(stream);

		struct dwbc *dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];

		dwb->otg_inst = stream_status->primary_otg_inst;

	}

	if (IS_DIAG_DC(dc->ctx->dce_environment)) {

		if (!dc->hwss.update_bandwidth(dc, dc->current_state)) {

			dm_error("DC: update_bandwidth failed!\n");

			return false;
@@ -413,18 +419,17 @@ bool dc_stream_add_writeback(struct dc *dc, 


		/* enable writeback */

		if (dc->hwss.enable_writeback) {

		struct dc_stream_status *stream_status = dc_stream_get_status(stream);

			struct dwbc *dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];



			if (dwb->funcs->is_enabled(dwb)) {

				/* writeback pipe already enabled, only need to update */

			dc->hwss.update_writeback(dc, stream_status, wb_info, dc->current_state);

				dc->hwss.update_writeback(dc, wb_info, dc->current_state);

			} else {

				/* Enable writeback pipe from scratch*/

			dc->hwss.enable_writeback(dc, stream_status, wb_info, dc->current_state);

				dc->hwss.enable_writeback(dc, wb_info, dc->current_state);

			}

		}

	}



	return true;

}
@@ -463,6 +468,7 @@ bool dc_stream_remove_writeback(struct dc *dc, 
	}

	stream->num_wb_info = j;



	if (IS_DIAG_DC(dc->ctx->dce_environment)) {

		/* recalculate and apply DML parameters */

		if (!dc->hwss.update_bandwidth(dc, dc->current_state)) {

			dm_error("DC: update_bandwidth failed!\n");
@@ -472,10 +478,19 @@ bool dc_stream_remove_writeback(struct dc *dc, 
		/* disable writeback */

		if (dc->hwss.disable_writeback)

			dc->hwss.disable_writeback(dc, dwb_pipe_inst);



	}

	return true;

}



bool dc_stream_warmup_writeback(struct dc *dc,

		int num_dwb,

		struct dc_writeback_info *wb_info)

{

	if (dc->hwss.mmhubbub_warmup)

		return dc->hwss.mmhubbub_warmup(dc, num_dwb, wb_info);

	else

		return false;

}

uint32_t dc_stream_get_vblank_counter(const struct dc_stream_state *stream)

{

	uint8_t i;

drivers/gpu/drm/amd/display/dc/dc_stream.h

+7 −0
Original line number Diff line number Diff line
@@ -344,10 +344,17 @@ bool dc_add_all_planes_for_stream( 
bool dc_stream_add_writeback(struct dc *dc,

		struct dc_stream_state *stream,

		struct dc_writeback_info *wb_info);



bool dc_stream_remove_writeback(struct dc *dc,

		struct dc_stream_state *stream,

		uint32_t dwb_pipe_inst);



bool dc_stream_warmup_writeback(struct dc *dc,

		int num_dwb,

		struct dc_writeback_info *wb_info);



bool dc_stream_dmdata_status_done(struct dc *dc, struct dc_stream_state *stream);



bool dc_stream_set_dynamic_metadata(struct dc *dc,

		struct dc_stream_state *stream,

		struct dc_dmdata_attributes *dmdata_attr);

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c

+1 −3
Original line number Diff line number Diff line
@@ -1740,7 +1740,6 @@ bool dcn20_update_bandwidth( 


void dcn20_enable_writeback(

		struct dc *dc,

		const struct dc_stream_status *stream_status,

		struct dc_writeback_info *wb_info,

		struct dc_state *context)

{
@@ -1754,8 +1753,7 @@ void dcn20_enable_writeback( 
	mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst];



	/* set the OPTC source mux */

	ASSERT(stream_status->primary_otg_inst < MAX_PIPES);

	optc = dc->res_pool->timing_generators[stream_status->primary_otg_inst];

	optc = dc->res_pool->timing_generators[dwb->otg_inst];

	optc->funcs->set_dwb_source(optc, wb_info->dwb_pipe_inst);

	/* set MCIF_WB buffer and arbitration configuration */

	mcif_wb->funcs->config_mcif_buf(mcif_wb, &wb_info->mcif_buf_params, wb_info->dwb_params.dest_height);

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h

+0 −1
Original line number Diff line number Diff line
@@ -104,7 +104,6 @@ void dcn20_program_triple_buffer( 
	bool enable_triple_buffer);

void dcn20_enable_writeback(

		struct dc *dc,

		const struct dc_stream_status *stream_status,

		struct dc_writeback_info *wb_info,

		struct dc_state *context);

void dcn20_disable_writeback(

drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h

+2 −1
Original line number Diff line number Diff line
@@ -113,7 +113,8 @@ struct dwbc { 
	int wb_src_plane_inst;/*hubp, mpcc, inst*/

	bool update_privacymask;

	uint32_t mask_id;



        int otg_inst;

        bool mvc_cfg;

};



struct dwbc_funcs {