Commit 6a7fde43 authored by George Shen's avatar George Shen Committed by Alex Deucher
Browse files

drm/amd/display: Update CR AUX RD interval interpretation 



[Why]
DP spec updated to have the CR AUX RD interval match the EQ AUX RD
interval interpretation of DPCD 0000Eh/0220Eh for 8b/10b non-LTTPR mode
and LTTPR transparent mode cases.

[How]
Update interpretation of DPCD 0000Eh/0220Eh for CR AUX RD interval
during 8b/10b link training.

Reviewed-by: default avatarMichael Strauss <michael.strauss@amd.com>
Reviewed-by: default avatarWenjing Liu <wenjing.liu@amd.com>
Signed-off-by: default avatarGeorge Shen <george.shen@amd.com>
Signed-off-by: default avatarZaeem Mohamed <zaeem.mohamed@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent d8c782ca

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c

+5 −2
Original line number Diff line number Diff line
@@ -36,7 +36,8 @@ 
	link->ctx->logger



static int32_t get_cr_training_aux_rd_interval(struct dc_link *link,

		const struct dc_link_settings *link_settings)

		const struct dc_link_settings *link_settings,

		enum lttpr_mode lttpr_mode)

{

	union training_aux_rd_interval training_rd_interval;

	uint32_t wait_in_micro_secs = 100;
@@ -49,6 +50,8 @@ static int32_t get_cr_training_aux_rd_interval(struct dc_link *link, 
				DP_TRAINING_AUX_RD_INTERVAL,

				(uint8_t *)&training_rd_interval,

				sizeof(training_rd_interval));

		if (lttpr_mode != LTTPR_MODE_NON_TRANSPARENT)

			wait_in_micro_secs = 400;

		if (training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL)

			wait_in_micro_secs = training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL * 4000;

	}
@@ -110,7 +113,6 @@ void decide_8b_10b_training_settings( 
	 */

	lt_settings->link_settings.link_spread = link->dp_ss_off ?

			LINK_SPREAD_DISABLED : LINK_SPREAD_05_DOWNSPREAD_30KHZ;

	lt_settings->cr_pattern_time = get_cr_training_aux_rd_interval(link, link_setting);

	lt_settings->eq_pattern_time = get_eq_training_aux_rd_interval(link, link_setting);

	lt_settings->pattern_for_cr = decide_cr_training_pattern(link_setting);

	lt_settings->pattern_for_eq = decide_eq_training_pattern(link, link_setting);
@@ -119,6 +121,7 @@ void decide_8b_10b_training_settings( 
	lt_settings->disallow_per_lane_settings = true;

	lt_settings->always_match_dpcd_with_hw_lane_settings = true;

	lt_settings->lttpr_mode = dp_decide_8b_10b_lttpr_mode(link);

	lt_settings->cr_pattern_time = get_cr_training_aux_rd_interval(link, link_setting, lt_settings->lttpr_mode);

	dp_hw_to_dpcd_lane_settings(lt_settings, lt_settings->hw_lane_settings, lt_settings->dpcd_lane_settings);

}