Commit 6a878a54 authored by Sricharan Ramabadhran's avatar Sricharan Ramabadhran Committed by Bjorn Helgaas
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PCI: qcom: Fix IPQ8074 enumeration 

PARF_SLV_ADDR_SPACE_SIZE_2_3_3 is used by qcom_pcie_post_init_2_3_3().
This PCIe slave address space size register offset is 0x358 but was
incorrectly changed to 0x16c by 39171b33 ("PCI: qcom: Remove PCIE20_
prefix from register definitions").

This prevented access to slave address space registers like iATU, etc.,
so the IPQ8074 PCIe controller was not enumerated.

Revert back to the correct 0x358 offset and remove the unused
PARF_SLV_ADDR_SPACE_SIZE_2_3_3.

Fixes: 39171b33 ("PCI: qcom: Remove PCIE20_ prefix from register definitions")
Link: https://lore.kernel.org/r/20230919102948.1844909-1-quic_srichara@quicinc.com


Tested-by: default avatarRobert Marko <robimarko@gmail.com>
Signed-off-by: default avatarSricharan Ramabadhran <quic_srichara@quicinc.com>
[bhelgaas: commit log]
Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: default avatarManivannan Sadhasivam <mani@kernel.org>
Reviewed-by: default avatarKonrad Dybcio <konrad.dybcio@linaro.org>
Cc: stable@vger.kernel.org	# v6.4+
parent 0bb80ecc

drivers/pci/controller/dwc/pcie-qcom.c

+1 −3
Original line number Diff line number Diff line
@@ -43,7 +43,6 @@ 
#define PARF_PHY_REFCLK				0x4c

#define PARF_CONFIG_BITS			0x50

#define PARF_DBI_BASE_ADDR			0x168

#define PARF_SLV_ADDR_SPACE_SIZE_2_3_3		0x16c /* Register offset specific to IP ver 2.3.3 */

#define PARF_MHI_CLOCK_RESET_CTRL		0x174

#define PARF_AXI_MSTR_WR_ADDR_HALT		0x178

#define PARF_AXI_MSTR_WR_ADDR_HALT_V2		0x1a8
@@ -797,8 +796,7 @@ static int qcom_pcie_post_init_2_3_3(struct qcom_pcie *pcie) 
	u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);

	u32 val;



	writel(SLV_ADDR_SPACE_SZ,

		pcie->parf + PARF_SLV_ADDR_SPACE_SIZE_2_3_3);

	writel(SLV_ADDR_SPACE_SZ, pcie->parf + PARF_SLV_ADDR_SPACE_SIZE);



	val = readl(pcie->parf + PARF_PHY_CTRL);

	val &= ~PHY_TEST_PWR_DOWN;