Commit 6aaff215 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-next-2023-12-18' of git://anongit.freedesktop.org/drm/drm-intel into drm-next 



- Drop pointless null checks and fix a scaler bug (Ville)
- Meteor Lake display fixes and clean-ups (RK, Jani, Andrzej, Mika, Imre)
- Clean-up around flip done IRQ (Ville)
- Fix eDP Meteor Lake bug (Jani)
- Bigjoiner fixes (Ankit, Ville)
- Cdclk/voltage_level cleanups and fixes (Ville)
- DMC event stuff (Ville)
- Remove dead code around intel_atomic_helper->free_list (Jouni)

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>

From: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/ZYB5XBRdWWgWoMKc@intel.com
parents 4f88cfd4 716c3cf2

drivers/gpu/drm/i915/display/i9xx_wm.c

+1 −1
Original line number Diff line number Diff line
@@ -608,7 +608,7 @@ static bool intel_crtc_active(struct intel_crtc *crtc) 
	 * crtc->state->active once we have proper CRTC states wired up

	 * for atomic.

	 */

	return crtc && crtc->active && crtc->base.primary->state->fb &&

	return crtc->active && crtc->base.primary->state->fb &&

		crtc->config->hw.adjusted_mode.crtc_clock;

}

drivers/gpu/drm/i915/display/intel_bios.c

+1 −2
Original line number Diff line number Diff line
@@ -3475,7 +3475,6 @@ bool intel_bios_get_dsc_params(struct intel_encoder *encoder, 
			if (!devdata->dsc)

				return false;



			if (crtc_state)

			fill_dsc(crtc_state, devdata->dsc, dsc_max_bpc);



			return true;

drivers/gpu/drm/i915/display/intel_cdclk.c

+69 −42
Original line number Diff line number Diff line
@@ -1180,7 +1180,7 @@ static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv) 
	/* force cdclk programming */

	dev_priv->display.cdclk.hw.cdclk = 0;

	/* force full PLL disable + enable */

	dev_priv->display.cdclk.hw.vco = -1;

	dev_priv->display.cdclk.hw.vco = ~0;

}



static void skl_cdclk_init_hw(struct drm_i915_private *dev_priv)
@@ -1446,50 +1446,77 @@ static u8 bxt_calc_voltage_level(int cdclk) 
	return DIV_ROUND_UP(cdclk, 25000);

}



static u8 calc_voltage_level(int cdclk, int num_voltage_levels,

			     const int voltage_level_max_cdclk[])

{

	int voltage_level;



	for (voltage_level = 0; voltage_level < num_voltage_levels; voltage_level++) {

		if (cdclk <= voltage_level_max_cdclk[voltage_level])

			return voltage_level;

	}



	MISSING_CASE(cdclk);

	return num_voltage_levels - 1;

}



static u8 icl_calc_voltage_level(int cdclk)

{

	if (cdclk > 556800)

		return 2;

	else if (cdclk > 312000)

		return 1;

	else

		return 0;

	static const int icl_voltage_level_max_cdclk[] = {

		[0] = 312000,

		[1] = 556800,

		[2] = 652800,

	};



	return calc_voltage_level(cdclk,

				  ARRAY_SIZE(icl_voltage_level_max_cdclk),

				  icl_voltage_level_max_cdclk);

}



static u8 ehl_calc_voltage_level(int cdclk)

{

	if (cdclk > 326400)

		return 3;

	else if (cdclk > 312000)

		return 2;

	else if (cdclk > 180000)

		return 1;

	else

		return 0;

	static const int ehl_voltage_level_max_cdclk[] = {

		[0] = 180000,

		[1] = 312000,

		[2] = 326400,

		/*

		 * Bspec lists the limit as 556.8 MHz, but some JSL

		 * development boards (at least) boot with 652.8 MHz

		 */

		[3] = 652800,

	};



	return calc_voltage_level(cdclk,

				  ARRAY_SIZE(ehl_voltage_level_max_cdclk),

				  ehl_voltage_level_max_cdclk);

}



static u8 tgl_calc_voltage_level(int cdclk)

{

	if (cdclk > 556800)

		return 3;

	else if (cdclk > 326400)

		return 2;

	else if (cdclk > 312000)

		return 1;

	else

		return 0;

	static const int tgl_voltage_level_max_cdclk[] = {

		[0] = 312000,

		[1] = 326400,

		[2] = 556800,

		[3] = 652800,

	};



	return calc_voltage_level(cdclk,

				  ARRAY_SIZE(tgl_voltage_level_max_cdclk),

				  tgl_voltage_level_max_cdclk);

}



static u8 rplu_calc_voltage_level(int cdclk)

{

	if (cdclk > 556800)

		return 3;

	else if (cdclk > 480000)

		return 2;

	else if (cdclk > 312000)

		return 1;

	else

		return 0;

	static const int rplu_voltage_level_max_cdclk[] = {

		[0] = 312000,

		[1] = 480000,

		[2] = 556800,

		[3] = 652800,

	};



	return calc_voltage_level(cdclk,

				  ARRAY_SIZE(rplu_voltage_level_max_cdclk),

				  rplu_voltage_level_max_cdclk);

}



static void icl_readout_refclk(struct drm_i915_private *dev_priv,
@@ -1800,6 +1827,8 @@ static bool cdclk_pll_is_unknown(unsigned int vco) 
	return vco == ~0;

}



static const int cdclk_squash_len = 16;



static int cdclk_squash_divider(u16 waveform)

{

	return hweight16(waveform ?: 0xffff);
@@ -1811,7 +1840,6 @@ static bool cdclk_compute_crawl_and_squash_midpoint(struct drm_i915_private *i91 
						    struct intel_cdclk_config *mid_cdclk_config)

{

	u16 old_waveform, new_waveform, mid_waveform;

	int size = 16;

	int div = 2;



	/* Return if PLL is in an unknown state, force a complete disable and re-enable. */
@@ -1850,7 +1878,8 @@ static bool cdclk_compute_crawl_and_squash_midpoint(struct drm_i915_private *i91 
	}



	mid_cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_squash_divider(mid_waveform) *

						    mid_cdclk_config->vco, size * div);

						    mid_cdclk_config->vco,

						    cdclk_squash_len * div);



	/* make sure the mid clock came out sane */
@@ -1878,9 +1907,9 @@ static void _bxt_set_cdclk(struct drm_i915_private *dev_priv, 
{

	int cdclk = cdclk_config->cdclk;

	int vco = cdclk_config->vco;

	u32 val;

	int unsquashed_cdclk;

	u16 waveform;

	int clock;

	u32 val;



	if (HAS_CDCLK_CRAWL(dev_priv) && dev_priv->display.cdclk.hw.vco > 0 && vco > 0 &&

	    !cdclk_pll_is_unknown(dev_priv->display.cdclk.hw.vco)) {
@@ -1897,15 +1926,13 @@ static void _bxt_set_cdclk(struct drm_i915_private *dev_priv, 


	waveform = cdclk_squash_waveform(dev_priv, cdclk);



	if (waveform)

		clock = vco / 2;

	else

		clock = cdclk;

	unsquashed_cdclk = DIV_ROUND_CLOSEST(cdclk * cdclk_squash_len,

					     cdclk_squash_divider(waveform));



	if (HAS_CDCLK_SQUASH(dev_priv))

		dg2_cdclk_squash_program(dev_priv, waveform);



	val = bxt_cdclk_cd2x_div_sel(dev_priv, clock, vco) |

	val = bxt_cdclk_cd2x_div_sel(dev_priv, unsquashed_cdclk, vco) |

		bxt_cdclk_cd2x_pipe(dev_priv, pipe);



	/*
@@ -2075,7 +2102,7 @@ static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv) 
	dev_priv->display.cdclk.hw.cdclk = 0;



	/* force full PLL disable + enable */

	dev_priv->display.cdclk.hw.vco = -1;

	dev_priv->display.cdclk.hw.vco = ~0;

}



static void bxt_cdclk_init_hw(struct drm_i915_private *dev_priv)
@@ -3489,7 +3516,7 @@ static const struct intel_cdclk_funcs mtl_cdclk_funcs = { 
	.get_cdclk = bxt_get_cdclk,

	.set_cdclk = bxt_set_cdclk,

	.modeset_calc_cdclk = bxt_modeset_calc_cdclk,

	.calc_voltage_level = tgl_calc_voltage_level,

	.calc_voltage_level = rplu_calc_voltage_level,

};



static const struct intel_cdclk_funcs rplu_cdclk_funcs = {

drivers/gpu/drm/i915/display/intel_crtc.c

+8 −1
Original line number Diff line number Diff line
@@ -553,8 +553,15 @@ void intel_pipe_update_start(struct intel_atomic_state *state, 


	intel_psr_lock(new_crtc_state);



	if (new_crtc_state->do_async_flip)

	if (new_crtc_state->do_async_flip) {

		spin_lock_irq(&crtc->base.dev->event_lock);

		/* arm the event for the flip done irq handler */

		crtc->flip_done_event = new_crtc_state->uapi.event;

		spin_unlock_irq(&crtc->base.dev->event_lock);



		new_crtc_state->uapi.event = NULL;

		return;

	}



	if (intel_crtc_needs_vblank_work(new_crtc_state))

		intel_crtc_vblank_work_init(new_crtc_state);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

+33 −49
Original line number Diff line number Diff line
@@ -745,7 +745,6 @@ static const struct intel_c10pll_state * const mtl_c10_edp_tables[] = { 


/* C20 basic DP 1.4 tables */

static const struct intel_c20pll_state mtl_c20_dp_rbr = {

	.link_bit_rate = 162000,

	.clock = 162000,

	.tx = {	0xbe88, /* tx cfg0 */

		0x5800, /* tx cfg1 */
@@ -771,7 +770,6 @@ static const struct intel_c20pll_state mtl_c20_dp_rbr = { 
};



static const struct intel_c20pll_state mtl_c20_dp_hbr1 = {

	.link_bit_rate = 270000,

	.clock = 270000,

	.tx = {	0xbe88, /* tx cfg0 */

		0x4800, /* tx cfg1 */
@@ -797,7 +795,6 @@ static const struct intel_c20pll_state mtl_c20_dp_hbr1 = { 
};



static const struct intel_c20pll_state mtl_c20_dp_hbr2 = {

	.link_bit_rate = 540000,

	.clock = 540000,

	.tx = {	0xbe88, /* tx cfg0 */

		0x4800, /* tx cfg1 */
@@ -823,7 +820,6 @@ static const struct intel_c20pll_state mtl_c20_dp_hbr2 = { 
};



static const struct intel_c20pll_state mtl_c20_dp_hbr3 = {

	.link_bit_rate = 810000,

	.clock = 810000,

	.tx = {	0xbe88, /* tx cfg0 */

		0x4800, /* tx cfg1 */
@@ -850,8 +846,7 @@ static const struct intel_c20pll_state mtl_c20_dp_hbr3 = { 


/* C20 basic DP 2.0 tables */

static const struct intel_c20pll_state mtl_c20_dp_uhbr10 = {

	.link_bit_rate = 1000000, /* 10 Gbps */

	.clock = 312500,

	.clock = 1000000, /* 10 Gbps */

	.tx = {	0xbe21, /* tx cfg0 */

		0x4800, /* tx cfg1 */

		0x0000, /* tx cfg2 */
@@ -875,8 +870,7 @@ static const struct intel_c20pll_state mtl_c20_dp_uhbr10 = { 
};



static const struct intel_c20pll_state mtl_c20_dp_uhbr13_5 = {

	.link_bit_rate = 1350000, /* 13.5 Gbps */

	.clock = 421875,

	.clock = 1350000, /* 13.5 Gbps */

	.tx = {	0xbea0, /* tx cfg0 */

		0x4800, /* tx cfg1 */

		0x0000, /* tx cfg2 */
@@ -901,8 +895,7 @@ static const struct intel_c20pll_state mtl_c20_dp_uhbr13_5 = { 
};



static const struct intel_c20pll_state mtl_c20_dp_uhbr20 = {

	.link_bit_rate = 2000000, /* 20 Gbps */

	.clock = 625000,

	.clock = 2000000, /* 20 Gbps */

	.tx = {	0xbe20, /* tx cfg0 */

		0x4800, /* tx cfg1 */

		0x0000, /* tx cfg2 */
@@ -1521,7 +1514,6 @@ static const struct intel_c10pll_state * const mtl_c10_hdmi_tables[] = { 
};



static const struct intel_c20pll_state mtl_c20_hdmi_25_175 = {

	.link_bit_rate = 25175,

	.clock = 25175,

	.tx = {  0xbe88, /* tx cfg0 */

		  0x9800, /* tx cfg1 */
@@ -1547,7 +1539,6 @@ static const struct intel_c20pll_state mtl_c20_hdmi_25_175 = { 
};



static const struct intel_c20pll_state mtl_c20_hdmi_27_0 = {

	.link_bit_rate = 27000,

	.clock = 27000,

	.tx = {  0xbe88, /* tx cfg0 */

		  0x9800, /* tx cfg1 */
@@ -1573,7 +1564,6 @@ static const struct intel_c20pll_state mtl_c20_hdmi_27_0 = { 
};



static const struct intel_c20pll_state mtl_c20_hdmi_74_25 = {

	.link_bit_rate = 74250,

	.clock = 74250,

	.tx = {  0xbe88, /* tx cfg0 */

		  0x9800, /* tx cfg1 */
@@ -1599,7 +1589,6 @@ static const struct intel_c20pll_state mtl_c20_hdmi_74_25 = { 
};



static const struct intel_c20pll_state mtl_c20_hdmi_148_5 = {

	.link_bit_rate = 148500,

	.clock = 148500,

	.tx = {  0xbe88, /* tx cfg0 */

		  0x9800, /* tx cfg1 */
@@ -1625,7 +1614,6 @@ static const struct intel_c20pll_state mtl_c20_hdmi_148_5 = { 
};



static const struct intel_c20pll_state mtl_c20_hdmi_594 = {

	.link_bit_rate = 594000,

	.clock = 594000,

	.tx = {  0xbe88, /* tx cfg0 */

		  0x9800, /* tx cfg1 */
@@ -1651,8 +1639,7 @@ static const struct intel_c20pll_state mtl_c20_hdmi_594 = { 
};



static const struct intel_c20pll_state mtl_c20_hdmi_300 = {

	.link_bit_rate = 3000000,

	.clock = 166670,

	.clock = 3000000,

	.tx = {  0xbe98, /* tx cfg0 */

		  0x9800, /* tx cfg1 */

		  0x0000, /* tx cfg2 */
@@ -1677,8 +1664,7 @@ static const struct intel_c20pll_state mtl_c20_hdmi_300 = { 
};



static const struct intel_c20pll_state mtl_c20_hdmi_600 = {

	.link_bit_rate = 6000000,

	.clock = 333330,

	.clock = 6000000,

	.tx = {  0xbe98, /* tx cfg0 */

		  0x9800, /* tx cfg1 */

		  0x0000, /* tx cfg2 */
@@ -1703,8 +1689,7 @@ static const struct intel_c20pll_state mtl_c20_hdmi_600 = { 
};



static const struct intel_c20pll_state mtl_c20_hdmi_800 = {

	.link_bit_rate = 8000000,

	.clock = 444440,

	.clock = 8000000,

	.tx = {  0xbe98, /* tx cfg0 */

		  0x9800, /* tx cfg1 */

		  0x0000, /* tx cfg2 */
@@ -1729,8 +1714,7 @@ static const struct intel_c20pll_state mtl_c20_hdmi_800 = { 
};



static const struct intel_c20pll_state mtl_c20_hdmi_1000 = {

	.link_bit_rate = 10000000,

	.clock = 555560,

	.clock = 10000000,

	.tx = {  0xbe98, /* tx cfg0 */

		  0x9800, /* tx cfg1 */

		  0x0000, /* tx cfg2 */
@@ -1755,8 +1739,7 @@ static const struct intel_c20pll_state mtl_c20_hdmi_1000 = { 
};



static const struct intel_c20pll_state mtl_c20_hdmi_1200 = {

	.link_bit_rate = 12000000,

	.clock = 666670,

	.clock = 12000000,

	.tx = {  0xbe98, /* tx cfg0 */

		  0x9800, /* tx cfg1 */

		  0x0000, /* tx cfg2 */
@@ -2005,7 +1988,6 @@ static int intel_c20_compute_hdmi_tmds_pll(u64 pixel_clock, struct intel_c20pll_ 
	else

		mpllb_ana_freq_vco = MPLLB_ANA_FREQ_VCO_0;



	pll_state->link_bit_rate	= pixel_clock;

	pll_state->clock	= pixel_clock;

	pll_state->tx[0]	= 0xbe88;

	pll_state->tx[1]	= 0x9800;
@@ -2042,7 +2024,7 @@ static int intel_c20_phy_check_hdmi_link_rate(int clock) 
	int i;



	for (i = 0; tables[i]; i++) {

		if (clock == tables[i]->link_bit_rate)

		if (clock == tables[i]->clock)

			return MODE_OK;

	}
@@ -2094,7 +2076,7 @@ static int intel_c20pll_calc_state(struct intel_crtc_state *crtc_state, 
		return -EINVAL;



	for (i = 0; tables[i]; i++) {

		if (crtc_state->port_clock == tables[i]->link_bit_rate) {

		if (crtc_state->port_clock == tables[i]->clock) {

			crtc_state->cx0pll_state.c20 = *tables[i];

			return 0;

		}
@@ -2117,7 +2099,7 @@ int intel_cx0pll_calc_state(struct intel_crtc_state *crtc_state, 
static bool intel_c20_use_mplla(u32 clock)

{

	/* 10G and 20G rates use MPLLA */

	if (clock == 312500 || clock == 625000)

	if (clock == 1000000 || clock == 2000000)

		return true;



	return false;
@@ -2220,11 +2202,11 @@ static u8 intel_c20_get_dp_rate(u32 clock) 
		return 6;

	case 432000: /* 4.32 Gbps eDP */

		return 7;

	case 312500: /* 10 Gbps DP2.0 */

	case 1000000: /* 10 Gbps DP2.0 */

		return 8;

	case 421875: /* 13.5 Gbps DP2.0 */

	case 1350000: /* 13.5 Gbps DP2.0 */

		return 9;

	case 625000: /* 20 Gbps DP2.0*/

	case 2000000: /* 20 Gbps DP2.0 */

		return 10;

	case 648000: /* 6.48 Gbps eDP*/

		return 11;
@@ -2242,13 +2224,13 @@ static u8 intel_c20_get_hdmi_rate(u32 clock) 
		return 0;



	switch (clock) {

	case 166670: /* 3 Gbps */

	case 333330: /* 6 Gbps */

	case 666670: /* 12 Gbps */

	case 300000: /* 3 Gbps */

	case 600000: /* 6 Gbps */

	case 1200000: /* 12 Gbps */

		return 1;

	case 444440: /* 8 Gbps */

	case 800000: /* 8 Gbps */

		return 2;

	case 555560: /* 10 Gbps */

	case 1000000: /* 10 Gbps */

		return 3;

	default:

		MISSING_CASE(clock);
@@ -2259,7 +2241,7 @@ static u8 intel_c20_get_hdmi_rate(u32 clock) 
static bool is_dp2(u32 clock)

{

	/* DP2.0 clock rates */

	if (clock == 312500 || clock == 421875 || clock  == 625000)

	if (clock == 1000000 || clock == 1350000 || clock  == 2000000)

		return true;



	return false;
@@ -2268,11 +2250,11 @@ static bool is_dp2(u32 clock) 
static bool is_hdmi_frl(u32 clock)

{

	switch (clock) {

	case 166670: /* 3 Gbps */

	case 333330: /* 6 Gbps */

	case 444440: /* 8 Gbps */

	case 555560: /* 10 Gbps */

	case 666670: /* 12 Gbps */

	case 300000: /* 3 Gbps */

	case 600000: /* 6 Gbps */

	case 800000: /* 8 Gbps */

	case 1000000: /* 10 Gbps */

	case 1200000: /* 12 Gbps */

		return true;

	default:

		return false;
@@ -2305,6 +2287,7 @@ static void intel_c20_pll_program(struct drm_i915_private *i915, 
	const struct intel_c20pll_state *pll_state = &crtc_state->cx0pll_state.c20;

	bool dp = false;

	int lane = crtc_state->lane_count > 2 ? INTEL_CX0_BOTH_LANES : INTEL_CX0_LANE0;

	u32 clock = crtc_state->port_clock;

	bool cntx;

	int i;
@@ -2343,7 +2326,7 @@ static void intel_c20_pll_program(struct drm_i915_private *i915, 
	}



	/* 3.3 mpllb or mplla configuration */

	if (intel_c20_use_mplla(pll_state->clock)) {

	if (intel_c20_use_mplla(clock)) {

		for (i = 0; i < ARRAY_SIZE(pll_state->mplla); i++) {

			if (cntx)

				intel_c20_sram_write(i915, encoder->port, INTEL_CX0_LANE0,
@@ -2370,23 +2353,23 @@ static void intel_c20_pll_program(struct drm_i915_private *i915, 
	/* 4. Program custom width to match the link protocol */

	intel_cx0_rmw(i915, encoder->port, lane, PHY_C20_VDR_CUSTOM_WIDTH,

		      PHY_C20_CUSTOM_WIDTH_MASK,

		      PHY_C20_CUSTOM_WIDTH(intel_get_c20_custom_width(pll_state->clock, dp)),

		      PHY_C20_CUSTOM_WIDTH(intel_get_c20_custom_width(clock, dp)),

		      MB_WRITE_COMMITTED);



	/* 5. For DP or 6. For HDMI */

	if (dp) {

		intel_cx0_rmw(i915, encoder->port, lane, PHY_C20_VDR_CUSTOM_SERDES_RATE,

			      BIT(6) | PHY_C20_CUSTOM_SERDES_MASK,

			      BIT(6) | PHY_C20_CUSTOM_SERDES(intel_c20_get_dp_rate(pll_state->clock)),

			      BIT(6) | PHY_C20_CUSTOM_SERDES(intel_c20_get_dp_rate(clock)),

			      MB_WRITE_COMMITTED);

	} else {

		intel_cx0_rmw(i915, encoder->port, lane, PHY_C20_VDR_CUSTOM_SERDES_RATE,

			      BIT(7) | PHY_C20_CUSTOM_SERDES_MASK,

			      is_hdmi_frl(pll_state->clock) ? BIT(7) : 0,

			      is_hdmi_frl(clock) ? BIT(7) : 0,

			      MB_WRITE_COMMITTED);



		intel_cx0_write(i915, encoder->port, INTEL_CX0_BOTH_LANES, PHY_C20_VDR_HDMI_RATE,

				intel_c20_get_hdmi_rate(pll_state->clock),

				intel_c20_get_hdmi_rate(clock),

				MB_WRITE_COMMITTED);

	}
@@ -2485,7 +2468,8 @@ static void intel_program_port_clock_ctl(struct intel_encoder *encoder, 


	val |= XELPDP_FORWARD_CLOCK_UNGATE;



	if (is_hdmi_frl(crtc_state->port_clock))

	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) &&

	    is_hdmi_frl(crtc_state->port_clock))

		val |= XELPDP_DDI_CLOCK_SELECT(XELPDP_DDI_CLOCK_SELECT_DIV18CLK);

	else

		val |= XELPDP_DDI_CLOCK_SELECT(XELPDP_DDI_CLOCK_SELECT_MAXPCLK);