Commit 6ab3581a authored by Clément Le Goffic's avatar Clément Le Goffic Committed by Krzysztof Kozlowski
Browse files

dt-bindings: memory: factorise LPDDR channel binding into SDRAM channel 



LPDDR, DDR and so SDRAM channels exist and share the same properties, they
have a compatible, ranks, and an io-width.

Signed-off-by: default avatarClément Le Goffic <clement.legoffic@foss.st.com>
Reviewed-by: default avatarRob Herring (Arm) <robh@kernel.org>
Signed-off-by: default avatarClément Le Goffic <legoffic.clement@gmail.com>
Link: https://patch.msgid.link/20251118-b4-ddr-bindings-v9-3-a033ac5144da@gmail.com


Signed-off-by: default avatarKrzysztof Kozlowski <krzk@kernel.org>
parent b5c1a217

Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr-channel.yaml→Documentation/devicetree/bindings/memory-controllers/ddr/jedec,sdram-channel.yaml

+12 −11
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr-channel.yaml#

$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,sdram-channel.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: LPDDR channel with chip/rank topology description

title: SDRAM channel with chip/rank topology description



description:

  An LPDDR channel is a completely independent set of LPDDR pins (DQ, CA, CS,

  CK, etc.) that connect one or more LPDDR chips to a host system. The main

  purpose of this node is to overall LPDDR topology of the system, including the

  amount of individual LPDDR chips and the ranks per chip.

  A memory channel of SDRAM memory like DDR SDRAM or LPDDR SDRAM is a completely

  independent set of pins (DQ, CA, CS, CK, etc.) that connect one or more memory

  chips to a host system. The main purpose of this node is to overall memory

  topology of the system, including the amount of individual memory chips and

  the ranks per chip.



maintainers:

  - Julius Werner <jwerner@chromium.org>
@@ -26,14 +27,14 @@ properties: 
  io-width:

    description:

      The number of DQ pins in the channel. If this number is different

      from (a multiple of) the io-width of the LPDDR chip, that means that

      from (a multiple of) the io-width of the SDRAM chip, that means that

      multiple instances of that type of chip are wired in parallel on this

      channel (with the channel's DQ pins split up between the different

      chips, and the CA, CS, etc. pins of the different chips all shorted

      together).  This means that the total physical memory controlled by a

      channel is equal to the sum of the densities of each rank on the

      connected LPDDR chip, times the io-width of the channel divided by

      the io-width of the LPDDR chip.

      connected SDRAM chip, times the io-width of the channel divided by

      the io-width of the SDRAM chip.

    enum:

      - 8

      - 16
@@ -51,8 +52,8 @@ patternProperties: 
  "^rank@[0-9]+$":

    type: object

    description:

      Each physical LPDDR chip may have one or more ranks. Ranks are

      internal but fully independent sub-units of the chip. Each LPDDR bus

      Each physical SDRAM chip may have one or more ranks. Ranks are

      internal but fully independent sub-units of the chip. Each SDRAM bus

      transaction on the channel targets exactly one rank, based on the

      state of the CS pins. Different ranks may have different densities and

      timing requirements.