Commit 6b10371c authored by Petr Machata's avatar Petr Machata Committed by Jakub Kicinski
Browse files

mlxsw: reg: Add to SFMR register the fields related to CFF flood mode 



Add the field cff_mid_base, which specifies at which point in PGT the
per-FID flood table is stored. Add cff_prf_id, the profile ID, which
determines on which row of the flood table a flood vector can be found for
a given traffic type.

Signed-off-by: default avatarPetr Machata <petrm@nvidia.com>
Reviewed-by: default avatarAmit Cohen <amcohen@nvidia.com>
Reviewed-by: default avatarIdo Schimmel <idosch@nvidia.com>
Link: https://lore.kernel.org/r/3ad7ae38cf6534bedcd876f16090d109a814b3e3.1700503644.git.petrm@nvidia.com


Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parent 446bc1e9

drivers/net/ethernet/mellanox/mlxsw/reg.h

+20 −0
Original line number Diff line number Diff line
@@ -1944,6 +1944,26 @@ MLXSW_ITEM32(reg, sfmr, irif_v, 0x14, 24, 1); 
 */

MLXSW_ITEM32(reg, sfmr, irif, 0x14, 0, 16);



/* reg_sfmr_cff_mid_base

 * Pointer to PGT table.

 * Range: 0..(cap_max_pgt-1)

 * Access: RW

 *

 * Note: Reserved when SwitchX/-2 and Spectrum-1.

 * Supported when CONFIG_PROFILE.flood_mode = CFF.

 */

MLXSW_ITEM32(reg, sfmr, cff_mid_base, 0x20, 0, 16);



/* reg_sfmr_cff_prf_id

 * Compressed Fid Flooding profile_id

 * Range 0..(max_cap_nve_flood_prf-1)

 * Access: RW

 *

 * Note: Reserved when SwitchX/-2 and Spectrum-1

 * Supported only when CONFIG_PROFLE.flood_mode = CFF.

 */

MLXSW_ITEM32(reg, sfmr, cff_prf_id, 0x24, 0, 2);



/* reg_sfmr_smpe_valid

 * SMPE is valid.

 * Access: RW