Commit 6b85a7e1 authored by Gatien Chevallier's avatar Gatien Chevallier Committed by Herbert Xu
Browse files

hwrng: stm32 - implement STM32MP13x support 

The RNG present on STM32MP13x platforms introduces a customizable
configuration and the conditional reset.

STM32 RNG configuration should best fit the requirements of the
platform. Therefore, put a platform-specific RNG configuration
field in the platform data. Default RNG configuration for STM32MP13
is the NIST certified configuration [1].

While there, fix and the RNG init sequence to support all RNG
versions.

[1] https://csrc.nist.gov/projects/cryptographic-module-validation-program/entropy-validations/certificate/53



Signed-off-by: default avatarGatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: default avatarHerbert Xu <herbert@gondor.apana.org.au>
parent 18d9a826

drivers/char/hw_random/stm32-rng.c

+158 −64
Original line number Diff line number Diff line
@@ -20,6 +20,14 @@ 
#define RNG_CR			0x00

#define RNG_CR_RNGEN		BIT(2)

#define RNG_CR_CED		BIT(5)

#define RNG_CR_CONFIG1		GENMASK(11, 8)

#define RNG_CR_NISTC		BIT(12)

#define RNG_CR_CONFIG2		GENMASK(15, 13)

#define RNG_CR_CONFIG3		GENMASK(25, 20)

#define RNG_CR_CONDRST		BIT(30)

#define RNG_CR_CONFLOCK		BIT(31)

#define RNG_CR_ENTROPY_SRC_MASK	(RNG_CR_CONFIG1 | RNG_CR_NISTC | RNG_CR_CONFIG2 | RNG_CR_CONFIG3)

#define RNG_CR_CONFIG_MASK	(RNG_CR_ENTROPY_SRC_MASK | RNG_CR_CED)



#define RNG_SR		0x04

#define RNG_SR_SEIS	BIT(6)
@@ -28,11 +36,24 @@ 


#define RNG_DR			0x08



#define RNG_NSCR		0x0C

#define RNG_NSCR_MASK		GENMASK(17, 0)



#define RNG_HTCR		0x10



struct stm32_rng_data {

	u32	cr;

	u32	nscr;

	u32	htcr;

	bool	has_cond_reset;

};



struct stm32_rng_private {

	struct hwrng rng;

	void __iomem *base;

	struct clk *clk;

	struct reset_control *rst;

	const struct stm32_rng_data *data;

	bool ced;

};
@@ -87,76 +108,77 @@ static int stm32_rng_init(struct hwrng *rng) 
	struct stm32_rng_private *priv =

	    container_of(rng, struct stm32_rng_private, rng);

	int err;

	u32 reg;



	err = clk_prepare_enable(priv->clk);

	if (err)

		return err;



	if (priv->ced)

		writel_relaxed(RNG_CR_RNGEN, priv->base + RNG_CR);

	else

		writel_relaxed(RNG_CR_RNGEN | RNG_CR_CED,

			       priv->base + RNG_CR);



	/* clear error indicators */

	writel_relaxed(0, priv->base + RNG_SR);



	return 0;

}

	reg = readl_relaxed(priv->base + RNG_CR);



static void stm32_rng_cleanup(struct hwrng *rng)

{

	struct stm32_rng_private *priv =

	    container_of(rng, struct stm32_rng_private, rng);



	writel_relaxed(0, priv->base + RNG_CR);

	clk_disable_unprepare(priv->clk);

}

	/*

	 * Keep default RNG configuration if none was specified.

	 * 0 is an invalid value as it disables all entropy sources.

	 */

	if (priv->data->has_cond_reset && priv->data->cr) {

		reg &= ~RNG_CR_CONFIG_MASK;

		reg |= RNG_CR_CONDRST | (priv->data->cr & RNG_CR_ENTROPY_SRC_MASK);

		if (priv->ced)

			reg &= ~RNG_CR_CED;

		else

			reg |= RNG_CR_CED;

		writel_relaxed(reg, priv->base + RNG_CR);



static int stm32_rng_probe(struct platform_device *ofdev)

{

	struct device *dev = &ofdev->dev;

	struct device_node *np = ofdev->dev.of_node;

	struct stm32_rng_private *priv;

	struct resource *res;

		/* Health tests and noise control registers */

		writel_relaxed(priv->data->htcr, priv->base + RNG_HTCR);

		writel_relaxed(priv->data->nscr & RNG_NSCR_MASK, priv->base + RNG_NSCR);



	priv = devm_kzalloc(dev, sizeof(struct stm32_rng_private), GFP_KERNEL);

	if (!priv)

		return -ENOMEM;

		reg &= ~RNG_CR_CONDRST;

		reg |= RNG_CR_RNGEN;

		writel_relaxed(reg, priv->base + RNG_CR);



	priv->base = devm_platform_get_and_ioremap_resource(ofdev, 0, &res);

	if (IS_ERR(priv->base))

		return PTR_ERR(priv->base);

		err = readl_relaxed_poll_timeout_atomic(priv->base + RNG_CR, reg,

							(!(reg & RNG_CR_CONDRST)),

							10, 50000);

		if (err) {

			dev_err((struct device *)priv->rng.priv,

				"%s: timeout %x!\n", __func__, reg);

			return -EINVAL;

		}

	} else {

		/* Handle all RNG versions by checking if conditional reset should be set */

		if (priv->data->has_cond_reset)

			reg |= RNG_CR_CONDRST;



	priv->clk = devm_clk_get(&ofdev->dev, NULL);

	if (IS_ERR(priv->clk))

		return PTR_ERR(priv->clk);

		if (priv->ced)

			reg &= ~RNG_CR_CED;

		else

			reg |= RNG_CR_CED;



	priv->rst = devm_reset_control_get(&ofdev->dev, NULL);

	if (!IS_ERR(priv->rst)) {

		reset_control_assert(priv->rst);

		udelay(2);

		reset_control_deassert(priv->rst);

	}

		writel_relaxed(reg, priv->base + RNG_CR);



	priv->ced = of_property_read_bool(np, "clock-error-detect");

		if (priv->data->has_cond_reset)

			reg &= ~RNG_CR_CONDRST;



	dev_set_drvdata(dev, priv);

		reg |= RNG_CR_RNGEN;



	priv->rng.name = dev_driver_string(dev);

#ifndef CONFIG_PM

	priv->rng.init = stm32_rng_init;

	priv->rng.cleanup = stm32_rng_cleanup;

#endif

	priv->rng.read = stm32_rng_read;

	priv->rng.priv = (unsigned long) dev;

	priv->rng.quality = 900;

		writel_relaxed(reg, priv->base + RNG_CR);

	}



	pm_runtime_set_autosuspend_delay(dev, 100);

	pm_runtime_use_autosuspend(dev);

	pm_runtime_enable(dev);

	err = readl_relaxed_poll_timeout_atomic(priv->base + RNG_SR, reg,

						reg & RNG_SR_DRDY,

						10, 100000);

	if (err | (reg & ~RNG_SR_DRDY)) {

		clk_disable_unprepare(priv->clk);

		dev_err((struct device *)priv->rng.priv,

			"%s: timeout:%x SR: %x!\n", __func__, err, reg);

		return -EINVAL;

	}



	return devm_hwrng_register(dev, &priv->rng);

	return 0;

}



static int stm32_rng_remove(struct platform_device *ofdev)
@@ -169,18 +191,28 @@ static int stm32_rng_remove(struct platform_device *ofdev) 
#ifdef CONFIG_PM

static int stm32_rng_runtime_suspend(struct device *dev)

{

	u32 reg;

	struct stm32_rng_private *priv = dev_get_drvdata(dev);



	stm32_rng_cleanup(&priv->rng);

	reg = readl_relaxed(priv->base + RNG_CR);

	reg &= ~RNG_CR_RNGEN;

	writel_relaxed(reg, priv->base + RNG_CR);

	clk_disable_unprepare(priv->clk);



	return 0;

}



static int stm32_rng_runtime_resume(struct device *dev)

{

	u32 reg;

	struct stm32_rng_private *priv = dev_get_drvdata(dev);



	return stm32_rng_init(&priv->rng);

	clk_prepare_enable(priv->clk);

	reg = readl_relaxed(priv->base + RNG_CR);

	reg |= RNG_CR_RNGEN;

	writel_relaxed(reg, priv->base + RNG_CR);



	return 0;

}

#endif
@@ -191,15 +223,77 @@ static const struct dev_pm_ops stm32_rng_pm_ops = { 
				pm_runtime_force_resume)

};



static const struct stm32_rng_data stm32mp13_rng_data = {

	.has_cond_reset = true,

	.cr = 0x00F00D00,

	.nscr = 0x2B5BB,

	.htcr = 0x969D,

};



static const struct stm32_rng_data stm32_rng_data = {

	.has_cond_reset = false,

};



static const struct of_device_id stm32_rng_match[] = {

	{

		.compatible = "st,stm32mp13-rng",

		.data = &stm32mp13_rng_data,

	},

	{

		.compatible = "st,stm32-rng",

		.data = &stm32_rng_data,

	},

	{},

};

MODULE_DEVICE_TABLE(of, stm32_rng_match);



static int stm32_rng_probe(struct platform_device *ofdev)

{

	struct device *dev = &ofdev->dev;

	struct device_node *np = ofdev->dev.of_node;

	struct stm32_rng_private *priv;

	struct resource *res;



	priv = devm_kzalloc(dev, sizeof(struct stm32_rng_private), GFP_KERNEL);

	if (!priv)

		return -ENOMEM;



	priv->base = devm_platform_get_and_ioremap_resource(ofdev, 0, &res);

	if (IS_ERR(priv->base))

		return PTR_ERR(priv->base);



	priv->clk = devm_clk_get(&ofdev->dev, NULL);

	if (IS_ERR(priv->clk))

		return PTR_ERR(priv->clk);



	priv->rst = devm_reset_control_get(&ofdev->dev, NULL);

	if (!IS_ERR(priv->rst)) {

		reset_control_assert(priv->rst);

		udelay(2);

		reset_control_deassert(priv->rst);

	}



	priv->ced = of_property_read_bool(np, "clock-error-detect");



	priv->data = of_device_get_match_data(dev);

	if (!priv->data)

		return -ENODEV;



	dev_set_drvdata(dev, priv);



	priv->rng.name = dev_driver_string(dev);

	priv->rng.init = stm32_rng_init;

	priv->rng.read = stm32_rng_read;

	priv->rng.priv = (unsigned long) dev;

	priv->rng.quality = 900;



	pm_runtime_set_autosuspend_delay(dev, 100);

	pm_runtime_use_autosuspend(dev);

	pm_runtime_enable(dev);



	return devm_hwrng_register(dev, &priv->rng);

}



static struct platform_driver stm32_rng_driver = {

	.driver = {

		.name = "stm32-rng",