Commit 6bbc69e5 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'socfpga_clk_updates_for_6.16_v2' of... 

Merge tag 'socfpga_clk_updates_for_6.16_v2' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into clk-socfpga

Pull SoCFPGA clk driver updates from Dinh Nguyen:

 - Optimize local variables for clocks

* tag 'socfpga_clk_updates_for_6.16_v2' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux:
  clk: socfpga: stratix10: Optimize local variables
  clk: socfpga: clk-pll: Optimize local variables
parents 0af2f6be 0248bfb2

drivers/clk/socfpga/clk-pll-s10.c

+3 −3
Original line number Diff line number Diff line
@@ -83,9 +83,9 @@ static unsigned long clk_pll_recalc_rate(struct clk_hw *hwclk, 
					 unsigned long parent_rate)

{

	struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk);

	unsigned long mdiv;

	unsigned long refdiv;

	unsigned long reg;

	u32 mdiv;

	u32 refdiv;

	u32 reg;

	unsigned long long vco_freq;



	/* read VCO1 reg for numerator and denominator */

drivers/clk/socfpga/clk-pll.c

+2 −2
Original line number Diff line number Diff line
@@ -39,9 +39,9 @@ static unsigned long clk_pll_recalc_rate(struct clk_hw *hwclk, 
					 unsigned long parent_rate)

{

	struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk);

	unsigned long divf, divq, reg;

	u32 divf, divq, reg;

	unsigned long long vco_freq;

	unsigned long bypass;

	u32 bypass;



	reg = readl(socfpgaclk->hw.reg);

	bypass = readl(clk_mgr_base_addr + CLKMGR_BYPASS);